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drm/amd/display: Fix MST recognizes connected displays as one

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[What]
MST now recognizes both connected displays

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Muhammad Ahmed 2023-08-23 19:25:25 -04:00 • committed by Alex Deucher
parent a6db1993c1
commit 7f7925e258
3 changed files with 20 additions and 20 deletions
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8
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View file

@ -1178,12 +1178,15 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
dto_params.otg_inst = tg->inst; dto_params.otg_inst = tg->inst;
dto_params.timing = &pipe_ctx->stream->timing; dto_params.timing = &pipe_ctx->stream->timing;
dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
if (dccg) {
dccg->funcs->set_dtbclk_dto(dccg, &dto_params); dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se) }
} else if (dccg && dccg->funcs->disable_symclk_se) {
dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
link_enc->transmitter - TRANSMITTER_UNIPHY_A); link_enc->transmitter - TRANSMITTER_UNIPHY_A);
}
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
/* TODO: This looks like a bug to me as we are disabling HPO IO when /* TODO: This looks like a bug to me as we are disabling HPO IO when
@ -2655,7 +2658,7 @@ void dce110_prepare_bandwidth(
struct clk_mgr *dccg = dc->clk_mgr; struct clk_mgr *dccg = dc->clk_mgr;
dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
if (dccg)
dccg->funcs->update_clocks( dccg->funcs->update_clocks(
dccg, dccg,
context, context,
@ -2670,6 +2673,7 @@ void dce110_optimize_bandwidth(
dce110_set_displaymarks(dc, context); dce110_set_displaymarks(dc, context);
if (dccg)
dccg->funcs->update_clocks( dccg->funcs->update_clocks(
dccg, dccg,
context, context,

8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View file

@ -2710,8 +2710,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
struct dce_hwseq *hws = dc->hwseq; struct dce_hwseq *hws = dc->hwseq;
unsigned int k1_div = PIXEL_RATE_DIV_NA; unsigned int k1_div = PIXEL_RATE_DIV_NA;
unsigned int k2_div = PIXEL_RATE_DIV_NA; unsigned int k2_div = PIXEL_RATE_DIV_NA;
struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
if (dc->hwseq->funcs.setup_hpo_hw_control) if (dc->hwseq->funcs.setup_hpo_hw_control)
@ -2731,10 +2729,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
dto_params.timing = &pipe_ctx->stream->timing; dto_params.timing = &pipe_ctx->stream->timing;
dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
dccg->funcs->set_dtbclk_dto(dccg, &dto_params); dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se) } else {
dccg->funcs->enable_symclk_se(dccg, }
stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);
if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
View file

@ -75,7 +75,7 @@ void mpc32_power_on_blnd_lut(
if (power_on) { if (power_on) {
REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0); REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5); REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
} else { } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
ASSERT(false); ASSERT(false);
/* TODO: change to mpc /* TODO: change to mpc
* dpp_base->ctx->dc->optimized_required = true; * dpp_base->ctx->dc->optimized_required = true;