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clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg

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The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-10-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Phil Edworthy 2022-05-03 12:55:54 +01:00 • committed by Geert Uytterhoeven
parent 63804400f2
commit 8090bea324
2 changed files with 17 additions and 3 deletions
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10
drivers/clk/renesas/rzg2l-cpg.c
View file

@ -1177,8 +1177,16 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->resets[id].off;
u32 bitmask = BIT(info->resets[id].bit);
s8 monbit = info->resets[id].monbit;
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
if (info->has_clk_mon_regs) {
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
} else if (monbit >= 0) {
u32 monbitmask = BIT(monbit);
return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
}
return -ENOTSUPP;
}
static const struct reset_control_ops rzg2l_cpg_reset_ops = {

10
drivers/clk/renesas/rzg2l-cpg.h
View file

@ -25,6 +25,7 @@
#define CPG_PL6_SSEL (0x414)
#define CPG_PL6_ETH_SSEL (0x418)
#define CPG_PL5_SDIV (0x420)
#define CPG_RST_MON (0x680)
#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
@ -206,17 +207,22 @@ struct rzg2l_mod_clk {
*
* @off: register offset
* @bit: reset bit
* @monbit: monitor bit in CPG_RST_MON register, -1 if none
*/
struct rzg2l_reset {
u16 off;
u8 bit;
s8 monbit;
};
#define DEF_RST(_id, _off, _bit) \
#define DEF_RST_MON(_id, _off, _bit, _monbit) \
[_id] = { \
.off = (_off), \
.bit = (_bit) \
.bit = (_bit), \
.monbit = (_monbit) \
}
#define DEF_RST(_id, _off, _bit) \
DEF_RST_MON(_id, _off, _bit, -1)
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description