ARM: at91: pm: avoid push and pop on stack while memory is in self-refersh
For the previous AT91 RAM controller and self-refresh procedure this had no side effects. However, for SAMA7G5 the self-refresh procedure doesn't allow this anymore as the RAM controller ports are closed before switching it to self-refresh. This commits prepares the code for the following ones adding self-refresh and PM support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-8-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea
Nicolas Ferre
parent
29cdf077a9
commit
87e1b30c29
1 changed files with 206 additions and 193 deletions
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@ -75,98 +75,147 @@ tmp3 .req r6
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.arm
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.arm
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/*
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/**
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* void at91_suspend_sram_fn(struct at91_pm_data*)
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* Enable self-refresh
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* @input param:
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*
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* @r0: base address of struct at91_pm_data
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* register usage:
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* @r1: memory type
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* @r2: base address of the sram controller
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* @r3: temporary
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*/
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*/
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/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
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.macro at91_sramc_self_refresh_ena
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.align 3
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ldr r1, .memtype
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ENTRY(at91_pm_suspend_in_sram)
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ldr r2, .sramc_base
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/* Save registers on stack */
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stmfd sp!, {r4 - r12, lr}
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/* Drain write buffer */
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cmp r1, #AT91_MEMCTRL_MC
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mov tmp1, #0
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bne sr_ena_ddrc_sf
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mcr p15, 0, tmp1, c7, c10, 4
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ldr tmp1, [r0, #PM_DATA_PMC]
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/* Active SDRAM self-refresh mode */
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str tmp1, .pmc_base
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mov r3, #1
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ldr tmp1, [r0, #PM_DATA_RAMC0]
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str r3, [r2, #AT91_MC_SDRAMC_SRR]
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str tmp1, .sramc_base
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b sr_ena_exit
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ldr tmp1, [r0, #PM_DATA_RAMC1]
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str tmp1, .sramc1_base
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ldr tmp1, [r0, #PM_DATA_MEMCTRL]
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str tmp1, .memtype
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ldr tmp1, [r0, #PM_DATA_MODE]
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str tmp1, .pm_mode
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ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
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str tmp1, .mckr_offset
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ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
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str tmp1, .pmc_version
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/* Both ldrne below are here to preload their address in the TLB */
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ldr tmp1, [r0, #PM_DATA_SHDWC]
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str tmp1, .shdwc
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0]
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ldr tmp1, [r0, #PM_DATA_SFRBU]
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str tmp1, .sfrbu
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0x10]
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/* Active the self-refresh mode */
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sr_ena_ddrc_sf:
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mov r0, #SRAMC_SELF_FRESH_ACTIVE
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cmp r1, #AT91_MEMCTRL_DDRSDR
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bl at91_sramc_self_refresh
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bne sr_ena_sdramc_sf
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ldr r0, .pm_mode
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/*
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cmp r0, #AT91_PM_STANDBY
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* DDR Memory controller
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beq standby
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*/
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cmp r0, #AT91_PM_BACKUP
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beq backup_mode
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bl at91_ulp_mode
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/* LPDDR1 --> force DDR2 mode during self-refresh */
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b exit_suspend
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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str r3, .saved_sam9_mdr
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bic r3, r3, #~AT91_DDRSDRC_MD
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cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq r3, [r2, #AT91_DDRSDRC_MDR]
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biceq r3, r3, #AT91_DDRSDRC_MD
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orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
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streq r3, [r2, #AT91_DDRSDRC_MDR]
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standby:
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/* Active DDRC self-refresh mode */
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/* Wait for interrupt */
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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ldr pmc, .pmc_base
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str r3, .saved_sam9_lpr
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at91_cpu_idle
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bic r3, r3, #AT91_DDRSDRC_LPCB
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b exit_suspend
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orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR]
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backup_mode:
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/* If using the 2nd ddr controller */
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bl at91_backup_mode
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ldr r2, .sramc1_base
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b exit_suspend
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cmp r2, #0
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beq sr_ena_no_2nd_ddrc
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exit_suspend:
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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/* Exit the self-refresh mode */
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str r3, .saved_sam9_mdr1
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mov r0, #SRAMC_SELF_FRESH_EXIT
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bic r3, r3, #~AT91_DDRSDRC_MD
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bl at91_sramc_self_refresh
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cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq r3, [r2, #AT91_DDRSDRC_MDR]
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biceq r3, r3, #AT91_DDRSDRC_MD
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orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
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streq r3, [r2, #AT91_DDRSDRC_MDR]
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/* Restore registers, and return */
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/* Active DDRC self-refresh mode */
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ldmfd sp!, {r4 - r12, pc}
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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ENDPROC(at91_pm_suspend_in_sram)
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str r3, .saved_sam9_lpr1
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bic r3, r3, #AT91_DDRSDRC_LPCB
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orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR]
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ENTRY(at91_backup_mode)
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sr_ena_no_2nd_ddrc:
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/* Switch the master clock source to slow clock. */
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b sr_ena_exit
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ldr pmc, .pmc_base
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ldr tmp2, .mckr_offset
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ldr tmp1, [pmc, tmp2]
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, tmp2]
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wait_mckrdy
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/*
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* SDRAMC Memory controller
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*/
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sr_ena_sdramc_sf:
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/* Active SDRAMC self-refresh mode */
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ldr r3, [r2, #AT91_SDRAMC_LPR]
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str r3, .saved_sam9_lpr
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bic r3, r3, #AT91_SDRAMC_LPCB
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orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_SDRAMC_LPR]
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/*BUMEN*/
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ldr r3, .saved_sam9_lpr
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ldr r0, .sfrbu
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str r3, [r2, #AT91_SDRAMC_LPR]
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mov tmp1, #0x1
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str tmp1, [r0, #0x10]
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/* Shutdown */
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sr_ena_exit:
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ldr r0, .shdwc
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.endm
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mov tmp1, #0xA5000000
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add tmp1, tmp1, #0x1
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/**
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str tmp1, [r0, #0]
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* Disable self-refresh
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ENDPROC(at91_backup_mode)
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*
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* register usage:
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* @r1: memory type
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* @r2: base address of the sram controller
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* @r3: temporary
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*/
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.macro at91_sramc_self_refresh_dis
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ldr r1, .memtype
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ldr r2, .sramc_base
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cmp r1, #AT91_MEMCTRL_MC
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bne sr_dis_ddrc_exit_sf
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/*
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* at91rm9200 Memory controller
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*/
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/*
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* For exiting the self-refresh mode, do nothing,
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* automatically exit the self-refresh mode.
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*/
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b sr_dis_exit
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sr_dis_ddrc_exit_sf:
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cmp r1, #AT91_MEMCTRL_DDRSDR
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bne sdramc_exit_sf
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/* DDR Memory controller */
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/* Restore MDR in case of LPDDR1 */
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ldr r3, .saved_sam9_mdr
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str r3, [r2, #AT91_DDRSDRC_MDR]
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/* Restore LPR on AT91 with DDRAM */
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_DDRSDRC_LPR]
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/* If using the 2nd ddr controller */
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ldr r2, .sramc1_base
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cmp r2, #0
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ldrne r3, .saved_sam9_mdr1
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strne r3, [r2, #AT91_DDRSDRC_MDR]
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ldrne r3, .saved_sam9_lpr1
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strne r3, [r2, #AT91_DDRSDRC_LPR]
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b sr_dis_exit
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sdramc_exit_sf:
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/* SDRAMC Memory controller */
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_SDRAMC_LPR]
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sr_dis_exit:
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.endm
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.macro at91_pm_ulp0_mode
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.macro at91_pm_ulp0_mode
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ldr pmc, .pmc_base
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ldr pmc, .pmc_base
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@ -503,7 +552,7 @@ ENDPROC(at91_backup_mode)
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2:
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2:
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.endm
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.endm
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ENTRY(at91_ulp_mode)
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.macro at91_ulp_mode
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ldr pmc, .pmc_base
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ldr pmc, .pmc_base
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ldr tmp2, .mckr_offset
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ldr tmp2, .mckr_offset
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ldr tmp3, .pm_mode
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ldr tmp3, .pm_mode
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@ -552,133 +601,97 @@ ulp_exit:
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wait_mckrdy
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wait_mckrdy
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mov pc, lr
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.endm
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ENDPROC(at91_ulp_mode)
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.macro at91_backup_mode
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/* Switch the master clock source to slow clock. */
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ldr pmc, .pmc_base
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ldr tmp2, .mckr_offset
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ldr tmp1, [pmc, tmp2]
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, tmp2]
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wait_mckrdy
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/*BUMEN*/
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ldr r0, .sfrbu
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mov tmp1, #0x1
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str tmp1, [r0, #0x10]
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/* Shutdown */
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ldr r0, .shdwc
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mov tmp1, #0xA5000000
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add tmp1, tmp1, #0x1
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str tmp1, [r0, #0]
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.endm
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/*
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/*
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* void at91_sramc_self_refresh(unsigned int is_active)
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* void at91_suspend_sram_fn(struct at91_pm_data*)
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*
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* @input param:
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* @input param:
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* @r0: 1 - active self-refresh mode
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* @r0: base address of struct at91_pm_data
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* 0 - exit self-refresh mode
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* register usage:
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* @r1: memory type
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* @r2: base address of the sram controller
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*/
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*/
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/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
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.align 3
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ENTRY(at91_pm_suspend_in_sram)
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/* Save registers on stack */
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stmfd sp!, {r4 - r12, lr}
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ENTRY(at91_sramc_self_refresh)
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/* Drain write buffer */
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ldr r1, .memtype
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mov tmp1, #0
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ldr r2, .sramc_base
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mcr p15, 0, tmp1, c7, c10, 4
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cmp r1, #AT91_MEMCTRL_MC
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ldr tmp1, [r0, #PM_DATA_PMC]
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bne ddrc_sf
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str tmp1, .pmc_base
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ldr tmp1, [r0, #PM_DATA_RAMC0]
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str tmp1, .sramc_base
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ldr tmp1, [r0, #PM_DATA_RAMC1]
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str tmp1, .sramc1_base
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ldr tmp1, [r0, #PM_DATA_MEMCTRL]
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str tmp1, .memtype
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ldr tmp1, [r0, #PM_DATA_MODE]
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str tmp1, .pm_mode
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ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
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str tmp1, .mckr_offset
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ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
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str tmp1, .pmc_version
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/* Both ldrne below are here to preload their address in the TLB */
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ldr tmp1, [r0, #PM_DATA_SHDWC]
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str tmp1, .shdwc
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0]
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ldr tmp1, [r0, #PM_DATA_SFRBU]
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str tmp1, .sfrbu
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0x10]
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/*
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/* Active the self-refresh mode */
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* at91rm9200 Memory controller
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at91_sramc_self_refresh_ena
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*/
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/*
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ldr r0, .pm_mode
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* For exiting the self-refresh mode, do nothing,
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cmp r0, #AT91_PM_STANDBY
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* automatically exit the self-refresh mode.
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beq standby
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*/
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cmp r0, #AT91_PM_BACKUP
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq backup_mode
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beq exit_sramc_sf
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/* Active SDRAM self-refresh mode */
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at91_ulp_mode
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mov r3, #1
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b exit_suspend
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str r3, [r2, #AT91_MC_SDRAMC_SRR]
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b exit_sramc_sf
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ddrc_sf:
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standby:
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cmp r1, #AT91_MEMCTRL_DDRSDR
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/* Wait for interrupt */
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bne sdramc_sf
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ldr pmc, .pmc_base
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at91_cpu_idle
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b exit_suspend
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/*
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backup_mode:
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* DDR Memory controller
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at91_backup_mode
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*/
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq ddrc_exit_sf
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/* LPDDR1 --> force DDR2 mode during self-refresh */
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exit_suspend:
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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/* Exit the self-refresh mode */
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str r3, .saved_sam9_mdr
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at91_sramc_self_refresh_dis
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bic r3, r3, #~AT91_DDRSDRC_MD
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cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq r3, [r2, #AT91_DDRSDRC_MDR]
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biceq r3, r3, #AT91_DDRSDRC_MD
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orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
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streq r3, [r2, #AT91_DDRSDRC_MDR]
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/* Active DDRC self-refresh mode */
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/* Restore registers, and return */
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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ldmfd sp!, {r4 - r12, pc}
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str r3, .saved_sam9_lpr
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ENDPROC(at91_pm_suspend_in_sram)
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bic r3, r3, #AT91_DDRSDRC_LPCB
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orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR]
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/* If using the 2nd ddr controller */
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ldr r2, .sramc1_base
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cmp r2, #0
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beq no_2nd_ddrc
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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str r3, .saved_sam9_mdr1
|
|
||||||
bic r3, r3, #~AT91_DDRSDRC_MD
|
|
||||||
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
|
||||||
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
|
|
||||||
biceq r3, r3, #AT91_DDRSDRC_MD
|
|
||||||
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
|
|
||||||
streq r3, [r2, #AT91_DDRSDRC_MDR]
|
|
||||||
|
|
||||||
/* Active DDRC self-refresh mode */
|
|
||||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
|
||||||
str r3, .saved_sam9_lpr1
|
|
||||||
bic r3, r3, #AT91_DDRSDRC_LPCB
|
|
||||||
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
|
||||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
|
||||||
|
|
||||||
no_2nd_ddrc:
|
|
||||||
b exit_sramc_sf
|
|
||||||
|
|
||||||
ddrc_exit_sf:
|
|
||||||
/* Restore MDR in case of LPDDR1 */
|
|
||||||
ldr r3, .saved_sam9_mdr
|
|
||||||
str r3, [r2, #AT91_DDRSDRC_MDR]
|
|
||||||
/* Restore LPR on AT91 with DDRAM */
|
|
||||||
ldr r3, .saved_sam9_lpr
|
|
||||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
|
||||||
|
|
||||||
/* If using the 2nd ddr controller */
|
|
||||||
ldr r2, .sramc1_base
|
|
||||||
cmp r2, #0
|
|
||||||
ldrne r3, .saved_sam9_mdr1
|
|
||||||
strne r3, [r2, #AT91_DDRSDRC_MDR]
|
|
||||||
ldrne r3, .saved_sam9_lpr1
|
|
||||||
strne r3, [r2, #AT91_DDRSDRC_LPR]
|
|
||||||
|
|
||||||
b exit_sramc_sf
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAMC Memory controller
|
|
||||||
*/
|
|
||||||
sdramc_sf:
|
|
||||||
tst r0, #SRAMC_SELF_FRESH_ACTIVE
|
|
||||||
beq sdramc_exit_sf
|
|
||||||
|
|
||||||
/* Active SDRAMC self-refresh mode */
|
|
||||||
ldr r3, [r2, #AT91_SDRAMC_LPR]
|
|
||||||
str r3, .saved_sam9_lpr
|
|
||||||
bic r3, r3, #AT91_SDRAMC_LPCB
|
|
||||||
orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
|
||||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
|
||||||
|
|
||||||
sdramc_exit_sf:
|
|
||||||
ldr r3, .saved_sam9_lpr
|
|
||||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
|
||||||
|
|
||||||
exit_sramc_sf:
|
|
||||||
mov pc, lr
|
|
||||||
ENDPROC(at91_sramc_self_refresh)
|
|
||||||
|
|
||||||
.pmc_base:
|
.pmc_base:
|
||||||
.word 0
|
.word 0
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue