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drm/msm/a6xx: Send ACD state to QMP at GMU resume

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The QMP mailbox expects to be notified of the ACD (Adaptive Clock
Distribution) state. Get a handle to the mailbox at probe time and
poke it at GMU resume.

Since we don't fully support ACD yet, hardcode the message to "val: 0"
(state = disabled).

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/559287/
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Konrad Dybcio 2023-09-25 16:50:35 +02:00 • committed by Rob Clark
parent af66706acc
commit 88a0997f2f
2 changed files with 18 additions and 0 deletions
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15
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View file

@ -989,6 +989,14 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
gmu->hung = false; gmu->hung = false;
/* Notify AOSS about the ACD state (unimplemented for now => disable it) */
if (!IS_ERR(gmu->qmp)) {
ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}",
0 /* Hardcode ACD to be disabled for now */);
if (ret)
dev_err(gmu->dev, "failed to send GPU ACD state\n");
}
/* Turn on the resources */ /* Turn on the resources */
pm_runtime_get_sync(gmu->dev); pm_runtime_get_sync(gmu->dev);
@ -1741,6 +1749,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
goto detach_cxpd; goto detach_cxpd;
} }
gmu->qmp = qmp_get(gmu->dev);
if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu))
return PTR_ERR(gmu->qmp);
init_completion(&gmu->pd_gate); init_completion(&gmu->pd_gate);
complete_all(&gmu->pd_gate); complete_all(&gmu->pd_gate);
gmu->pd_nb.notifier_call = cxpd_notifier_cb; gmu->pd_nb.notifier_call = cxpd_notifier_cb;
@ -1764,6 +1776,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
return 0; return 0;
if (!IS_ERR_OR_NULL(gmu->qmp))
qmp_put(gmu->qmp);
detach_cxpd: detach_cxpd:
dev_pm_domain_detach(gmu->cxpd, false); dev_pm_domain_detach(gmu->cxpd, false);

3
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
View file

@ -8,6 +8,7 @@
#include <linux/iopoll.h> #include <linux/iopoll.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/notifier.h> #include <linux/notifier.h>
#include <linux/soc/qcom/qcom_aoss.h>
#include "msm_drv.h" #include "msm_drv.h"
#include "a6xx_hfi.h" #include "a6xx_hfi.h"
@ -96,6 +97,8 @@ struct a6xx_gmu {
/* For power domain callback */ /* For power domain callback */
struct notifier_block pd_nb; struct notifier_block pd_nb;
struct completion pd_gate; struct completion pd_gate;
struct qmp *qmp;
}; };
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)