niansa-misc/linux
1
0
Fork 0
mirror of synced 2025-03-06 20:59:54 +01:00
Code Issues Projects Releases Packages Wiki Activity

x86/mce: Check whether writes to MCA_STATUS are getting ignored

Browse source 
The platform can sometimes - depending on its settings - cause writes
to MCA_STATUS MSRs to get ignored, regardless of HWCR[McStatusWrEn]'s
value.

For further info see

  PPR for AMD Family 19h, Model 01h, Revision B1 Processors, doc ID 55898

at https://bugzilla.kernel.org/show_bug.cgi?id=206537.

Therefore, probe for ignored writes to MCA_STATUS to determine if hardware
error injection is at all possible.

  [ bp: Heavily massage commit message and patch. ]

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220214233640.70510-2-Smita.KoralahalliChannabasappa@amd.com
This commit is contained in:
Smita Koralahalli 2022-06-27 20:56:46 +00:00 • committed by Borislav Petkov
parent a111daf0c5
commit 891e465a1b
2 changed files with 48 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

47
arch/x86/kernel/cpu/mce/inject.c
View file

@ -33,6 +33,8 @@
#include "internal.h" #include "internal.h"
static bool hw_injection_possible = true;
/* /*
* Collect all the MCi_XXX settings * Collect all the MCi_XXX settings
*/ */
@ -339,6 +341,8 @@ static int __set_inj(const char *buf)
for (i = 0; i < N_INJ_TYPES; i++) { for (i = 0; i < N_INJ_TYPES; i++) {
if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) { if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
if (i > SW_INJ && !hw_injection_possible)
continue;
inj_type = i; inj_type = i;
return 0; return 0;
} }
@ -717,11 +721,54 @@ static void __init debugfs_init(void)
&i_mce, dfs_fls[i].fops); &i_mce, dfs_fls[i].fops);
} }
static void check_hw_inj_possible(void)
{
int cpu;
u8 bank;
/*
* This behavior exists only on SMCA systems though its not directly
* related to SMCA.
*/
if (!cpu_feature_enabled(X86_FEATURE_SMCA))
return;
cpu = get_cpu();
for (bank = 0; bank < MAX_NR_BANKS; ++bank) {
u64 status = MCI_STATUS_VAL, ipid;
/* Check whether bank is populated */
rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), ipid);
if (!ipid)
continue;
toggle_hw_mce_inject(cpu, true);
wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status);
rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status);
if (!status) {
hw_injection_possible = false;
pr_warn("Platform does not allow *hardware* error injection."
"Try using APEI EINJ instead.\n");
}
toggle_hw_mce_inject(cpu, false);
break;
}
put_cpu();
}
static int __init inject_init(void) static int __init inject_init(void)
{ {
if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL)) if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL))
return -ENOMEM; return -ENOMEM;
check_hw_inj_possible();
debugfs_init(); debugfs_init();
register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify"); register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify");

2
arch/x86/kernel/cpu/mce/internal.h
View file

@ -211,7 +211,7 @@ noinstr u64 mce_rdmsrl(u32 msr);
static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg) static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
{ {
if (mce_flags.smca) { if (cpu_feature_enabled(X86_FEATURE_SMCA)) {
switch (reg) { switch (reg) {
case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank);
case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank);