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drm/i915/vdsc: Fill the intel_dsc_get_pps_config function

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We have setup both the read and write functions so we can
move ahead and fill in all the readout state from PPS register
into the crtc_state so we can send it for comparision.

--v2
-Shorten comment to just PPSX rather than having the whole
"Readout PPSX register" [Jani]
-Remove pps_temp reinitialization as its being initialized in
the read function [Jani]
-Use REG_FIELD_GET to readout certain fields of dsc registers
[Jani]

--v9
-Place the masks at a more appropriate place [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-8-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal 2023-08-28 11:13:00 +05:30 • committed by Animesh Manna
parent 961e11ab9f
commit 8b70b56917
2 changed files with 95 additions and 7 deletions
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100
drivers/gpu/drm/i915/display/intel_vdsc.c
View file

@ -852,20 +852,106 @@ static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_stat
static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
{
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
u32 pps_temp1, pps_temp2;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
u32 pps_temp;
/* FIXME: add more state readout as needed */
/* PPS_0 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp);
/* Readout PPS_0 and PPS_1 registers */
intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
vdsc_cfg->line_buf_depth =
(pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT;
vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION;
vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
vdsc_cfg->bits_per_pixel = pps_temp2;
/* PPS_1 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp);
if (pps_temp1 & DSC_NATIVE_420_ENABLE)
vdsc_cfg->bits_per_pixel = pps_temp;
if (vdsc_cfg->native_420)
vdsc_cfg->bits_per_pixel >>= 1;
crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
/* PPS_2 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;
vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
/* PPS_3 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp);
vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
/* PPS_4 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp);
vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
/* PPS_5 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp);
vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
/* PPS_6 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp);
vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
/* PPS_7 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp);
vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
/* PPS_8 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp);
vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
/* PPS_9 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp);
vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
/* PPS_10 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp);
vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
/* PPS_16 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp);
vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
if (DISPLAY_VER(i915) >= 14) {
/* PPS_17 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp);
vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
/* PPS_18 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp);
vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
}
}
void intel_dsc_get_config(struct intel_crtc_state *crtc_state)

2
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
View file

@ -81,7 +81,9 @@
#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
#define DSC_BLOCK_PREDICTION (1 << 16)
#define DSC_LINE_BUF_DEPTH_SHIFT 12
#define DSC_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12)
#define DSC_BPC_SHIFT 8
#define DSC_BPC_MASK REG_GENMASK(11, 8)
#define DSC_VER_MIN_SHIFT 4
#define DSC_VER_MAJ (0x1 << 0)