Memory controller drivers for v6.14 - TI
TI AEMIF driver enhancements: some refactoring around timing parameters and finally adding plus exporting interfaces for devices using the AEMIF interface (e.g. TI Davinci NAND controller) to better configure the memory interface. The exported functions are going to be used by: drivers/mtd/nand/raw/davinci_nand.c -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmddXowQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD15LAD/9E/LtoM//W6VHRIItF0AmYH7e2E4D2ECwl MQyLCsj4zieIg5TLlnZMC/P2P1BIZoerCPN4QC+M/r5NZrMfufZYNdlpY0sqpkd2 CoW2w8TjN+PHpzOGncHvbxdD5h/SHS0cRoOqiTJmZXeVf4FCq7riv8piGyoontNC puzsSjjCOk/AHMHsHBVB3/VbWelvQbjq/qKyW/+aWl8tw3W+Ck4qiPcUMWXkLHhx FfsrsUXWqOP7di2zcwWx4N+rNJWuYaM6xv6FoTlkVAhc094vDE/uKvBbQcizX/fd 1iMgUsvt6BpLGKbJ8G3ZBL/DY+ugJv5oC7Cql0AWi9/NjW/Yil9C2a0RqKl48TCW a4EeJrrXnocK5l0PDodQbyNL+D9c7tiwzs10/VEg2MnchaN8ZvdP/YfLICkJiXcF ZAio89mG6r/S/AAe05M1vKso1Le/D0Lhx5IiJ9MDnHvJ5Hw2JPnGs7Dcqq5Xm47K toY0kJmUfPZyAyavax7z1nGAAglpsXGN1m52AEoCcwMyU0DTamSUTf+a7pjKph78 jrv1g2MB06kjGhXVT//8fS07C5b0v/Rn5CB2LgakgGsug1g6+YD0/rAylGNUTjHX Dx9lVDz8llr68OP+bdUOTO9mlx+t1gI6SVg9U9gUKHbr95xVhMlyRuwwmqwdsPK8 U+8kZyAi9w== =uAGp -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmeHwhYACgkQYKtH/8kJ UidmTw//UEpTayeDW6qY7t55exNBe1CoZwXcRioyvBngXAbKzBG6sVZV2Z9NnMNB soSVSyiaNXv10zIxACEkVCrXExvbdoPPZ99rz7ZpZMjfltTRB5PnM0qjm8iouHc2 RoJ4abDKq/frEKpNhLNrDWOKaO+g4t/Scu+6DIYaIin/Ndaax/d8vS3H6dprohgK l9no/58tZmXOU8HMCk/MjH1c6QPKkU3eMx1yIkiuabbcpeY5glMiy1tM3m56SxOV UAgECchsCvFIbkvbo3XAIkqqmhSdt4eIpGAdNrKJbSGzeuAeUTyKjbTbeQRNpf8/ hcFVGv3E8uj/VDspHuX/bXNdQNvyl/XJi80Ztzs/HlFquqlX0zwx/uRqmFGq1muF 4QUzuVyEAxQjBECeuBVT4DVQyXU5fSfwZSptf7LiX6TF+oj9j++lPZSVgjFytQO8 nUhDxhf3ilcZCDSpKmQ1Cm01j7mHJarAdem5ac6E2jDX25PPZB48vjBugTbEi4q2 ShIsNyrVAhpI8frynv255ndBCWNvRKZ51HE2VxJSFRC2zusS0JYt6Bs8+q8zpA3L HwalWhojazKeY36hrE8B6R/PQ7YncXBtYP1A/gXO7jmTNAAAjCS0PqobcCI6xDZk 18+wWn+5F1X2mhUA04dM7WH0liVPdn2tJLEdx+zQpk1ChkLZE3U= =ELyQ -----END PGP SIGNATURE----- Merge tag 'memory-controller-drv-ti-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers Memory controller drivers for v6.14 - TI TI AEMIF driver enhancements: some refactoring around timing parameters and finally adding plus exporting interfaces for devices using the AEMIF interface (e.g. TI Davinci NAND controller) to better configure the memory interface. The exported functions are going to be used by: drivers/mtd/nand/raw/davinci_nand.c * tag 'memory-controller-drv-ti-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: ti-aemif: Export aemif_*_cs_timings() memory: ti-aemif: Create aemif_set_cs_timings() memory: ti-aemif: Create aemif_check_cs_timings() memory: ti-aemif: Wrap CS timings into a struct memory: ti-aemif: Remove unnecessary local variables memory: ti-aemif: Store timings parameter in number of cycles - 1 Link: https://lore.kernel.org/r/20241231133534.136771-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
8de2819d07
2 changed files with 148 additions and 76 deletions
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@ -13,7 +13,9 @@
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/memory/ti-aemif.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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@ -69,39 +71,27 @@
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#define ACR_SSTROBE_MASK BIT(31)
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#define ASIZE_16BIT 1
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#define CONFIG_MASK (TA(TA_MAX) | \
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RHOLD(RHOLD_MAX) | \
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RSTROBE(RSTROBE_MAX) | \
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RSETUP(RSETUP_MAX) | \
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WHOLD(WHOLD_MAX) | \
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WSTROBE(WSTROBE_MAX) | \
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WSETUP(WSETUP_MAX) | \
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EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \
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ASIZE_MAX)
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#define TIMINGS_MASK (TA(TA_MAX) | \
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RHOLD(RHOLD_MAX) | \
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RSTROBE(RSTROBE_MAX) | \
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RSETUP(RSETUP_MAX) | \
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WHOLD(WHOLD_MAX) | \
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WSTROBE(WSTROBE_MAX) | \
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WSETUP(WSETUP_MAX))
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#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX)
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/**
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* struct aemif_cs_data: structure to hold cs parameters
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* struct aemif_cs_data: structure to hold CS parameters
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* @timings: timings configuration
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* @cs: chip-select number
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* @wstrobe: write strobe width, ns
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* @rstrobe: read strobe width, ns
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* @wsetup: write setup width, ns
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* @whold: write hold width, ns
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* @rsetup: read setup width, ns
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* @rhold: read hold width, ns
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* @ta: minimum turn around time, ns
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* @enable_ss: enable/disable select strobe mode
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* @enable_ew: enable/disable extended wait mode
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* @asize: width of the asynchronous device's data bus
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*/
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struct aemif_cs_data {
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struct aemif_cs_timings timings;
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u8 cs;
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u16 wstrobe;
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u16 rstrobe;
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u8 wsetup;
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u8 whold;
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u8 rsetup;
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u8 rhold;
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u8 ta;
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u8 enable_ss;
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u8 enable_ew;
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u8 asize;
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@ -115,6 +105,7 @@ struct aemif_cs_data {
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* @num_cs: number of assigned chip-selects
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* @cs_offset: start number of cs nodes
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* @cs_data: array of chip-select settings
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* @config_cs_lock: lock used to access CS configuration
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*/
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struct aemif_device {
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void __iomem *base;
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@ -123,20 +114,94 @@ struct aemif_device {
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u8 num_cs;
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int cs_offset;
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struct aemif_cs_data cs_data[NUM_CS];
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struct mutex config_cs_lock;
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};
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/**
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* aemif_check_cs_timings() - Check the validity of a CS timing configuration.
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* @timings: timings configuration
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*
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* @return: 0 if the timing configuration is valid, negative error number otherwise.
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*/
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int aemif_check_cs_timings(struct aemif_cs_timings *timings)
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{
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if (timings->ta > TA_MAX)
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return -EINVAL;
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if (timings->rhold > RHOLD_MAX)
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return -EINVAL;
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if (timings->rstrobe > RSTROBE_MAX)
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return -EINVAL;
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if (timings->rsetup > RSETUP_MAX)
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return -EINVAL;
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if (timings->whold > WHOLD_MAX)
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return -EINVAL;
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if (timings->wstrobe > WSTROBE_MAX)
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return -EINVAL;
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if (timings->wsetup > WSETUP_MAX)
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return -EINVAL;
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return 0;
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}
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EXPORT_SYMBOL_GPL(aemif_check_cs_timings);
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/**
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* aemif_set_cs_timings() - Set the timing configuration of a given chip select.
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* @aemif: aemif device to configure
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* @cs: index of the chip select to configure
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* @timings: timings configuration to set
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*
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* @return: 0 on success, else negative errno.
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*/
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int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs,
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struct aemif_cs_timings *timings)
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{
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unsigned int offset;
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u32 val, set;
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int ret;
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if (!timings || !aemif)
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return -EINVAL;
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if (cs > aemif->num_cs)
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return -EINVAL;
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ret = aemif_check_cs_timings(timings);
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if (ret)
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return ret;
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set = TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrobe) |
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RSETUP(timings->rsetup) | WHOLD(timings->whold) |
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WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup);
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offset = A1CR_OFFSET + cs * 4;
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mutex_lock(&aemif->config_cs_lock);
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val = readl(aemif->base + offset);
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val &= ~TIMINGS_MASK;
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val |= set;
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writel(val, aemif->base + offset);
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mutex_unlock(&aemif->config_cs_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(aemif_set_cs_timings);
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/**
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* aemif_calc_rate - calculate timing data.
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* @pdev: platform device to calculate for
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* @wanted: The cycle time needed in nanoseconds.
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* @clk: The input clock rate in kHz.
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* @max: The maximum divider value that can be programmed.
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*
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* On success, returns the calculated timing value minus 1 for easy
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* programming into AEMIF timing registers, else negative errno.
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* @return: the calculated timing value minus 1 for easy
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* programming into AEMIF timing registers.
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*/
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static int aemif_calc_rate(struct platform_device *pdev, int wanted,
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unsigned long clk, int max)
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static u32 aemif_calc_rate(struct platform_device *pdev, int wanted, unsigned long clk)
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{
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int result;
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@ -149,10 +214,6 @@ static int aemif_calc_rate(struct platform_device *pdev, int wanted,
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if (result < 0)
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result = 0;
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/* ... But configuring tighter timings is not an option. */
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else if (result > max)
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result = -EINVAL;
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return result;
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}
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@ -174,48 +235,25 @@ static int aemif_config_abus(struct platform_device *pdev, int csnum)
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{
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struct aemif_device *aemif = platform_get_drvdata(pdev);
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struct aemif_cs_data *data = &aemif->cs_data[csnum];
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int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
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unsigned long clk_rate = aemif->clk_rate;
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unsigned offset;
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u32 set, val;
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offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
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ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
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rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
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rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
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rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
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whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
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wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX);
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wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX);
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if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
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whold < 0 || wstrobe < 0 || wsetup < 0) {
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dev_err(&pdev->dev, "%s: cannot get suitable timings\n",
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__func__);
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return -EINVAL;
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}
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set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
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WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
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set |= (data->asize & ACR_ASIZE_MASK);
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set = (data->asize & ACR_ASIZE_MASK);
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if (data->enable_ew)
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set |= ACR_EW_MASK;
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if (data->enable_ss)
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set |= ACR_SSTROBE_MASK;
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mutex_lock(&aemif->config_cs_lock);
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val = readl(aemif->base + offset);
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val &= ~CONFIG_MASK;
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val |= set;
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writel(val, aemif->base + offset);
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mutex_unlock(&aemif->config_cs_lock);
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return 0;
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}
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static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate)
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{
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return ((val + 1) * NSEC_PER_MSEC) / clk_rate;
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return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->timings);
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}
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/**
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@ -231,19 +269,18 @@ static void aemif_get_hw_params(struct platform_device *pdev, int csnum)
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{
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struct aemif_device *aemif = platform_get_drvdata(pdev);
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struct aemif_cs_data *data = &aemif->cs_data[csnum];
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unsigned long clk_rate = aemif->clk_rate;
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u32 val, offset;
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offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
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val = readl(aemif->base + offset);
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data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate);
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data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate);
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data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate);
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data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate);
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data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate);
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data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate);
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data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate);
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data->timings.ta = TA_VAL(val);
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data->timings.rhold = RHOLD_VAL(val);
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data->timings.rstrobe = RSTROBE_VAL(val);
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data->timings.rsetup = RSETUP_VAL(val);
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data->timings.whold = WHOLD_VAL(val);
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data->timings.wstrobe = WSTROBE_VAL(val);
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data->timings.wsetup = WSETUP_VAL(val);
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data->enable_ew = EW_VAL(val);
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data->enable_ss = SSTROBE_VAL(val);
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data->asize = val & ASIZE_MAX;
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@ -261,6 +298,7 @@ static int of_aemif_parse_abus_config(struct platform_device *pdev,
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struct device_node *np)
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{
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struct aemif_device *aemif = platform_get_drvdata(pdev);
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unsigned long clk_rate = aemif->clk_rate;
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struct aemif_cs_data *data;
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u32 cs;
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u32 val;
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@ -288,32 +326,33 @@ static int of_aemif_parse_abus_config(struct platform_device *pdev,
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/* override the values from device node */
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if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val))
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data->ta = val;
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data->timings.ta = aemif_calc_rate(pdev, val, clk_rate);
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if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val))
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data->rhold = val;
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data->timings.rhold = aemif_calc_rate(pdev, val, clk_rate);
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if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val))
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data->rstrobe = val;
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data->timings.rstrobe = aemif_calc_rate(pdev, val, clk_rate);
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if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val))
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data->rsetup = val;
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data->timings.rsetup = aemif_calc_rate(pdev, val, clk_rate);
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if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val))
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data->whold = val;
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data->timings.whold = aemif_calc_rate(pdev, val, clk_rate);
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if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val))
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data->wstrobe = val;
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data->timings.wstrobe = aemif_calc_rate(pdev, val, clk_rate);
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if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val))
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data->wsetup = val;
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data->timings.wsetup = aemif_calc_rate(pdev, val, clk_rate);
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if (!of_property_read_u32(np, "ti,cs-bus-width", &val))
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if (val == 16)
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data->asize = 1;
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data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode");
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data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode");
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return 0;
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return aemif_check_cs_timings(&data->timings);
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}
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static const struct of_device_id aemif_of_match[] = {
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@ -351,6 +390,7 @@ static int aemif_probe(struct platform_device *pdev)
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if (IS_ERR(aemif->base))
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return PTR_ERR(aemif->base);
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mutex_init(&aemif->config_cs_lock);
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if (np) {
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/*
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* For every controller device node, there is a cs device node
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32
include/linux/memory/ti-aemif.h
Normal file
32
include/linux/memory/ti-aemif.h
Normal file
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MEMORY_TI_AEMIF_H
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#define __MEMORY_TI_AEMIF_H
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/**
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* struct aemif_cs_timings: structure to hold CS timing configuration
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* values are expressed in number of clock cycles - 1
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* @ta: minimum turn around time
|
||||
* @rhold: read hold width
|
||||
* @rstrobe: read strobe width
|
||||
* @rsetup: read setup width
|
||||
* @whold: write hold width
|
||||
* @wstrobe: write strobe width
|
||||
* @wsetup: write setup width
|
||||
*/
|
||||
struct aemif_cs_timings {
|
||||
u32 ta;
|
||||
u32 rhold;
|
||||
u32 rstrobe;
|
||||
u32 rsetup;
|
||||
u32 whold;
|
||||
u32 wstrobe;
|
||||
u32 wsetup;
|
||||
};
|
||||
|
||||
struct aemif_device;
|
||||
|
||||
int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_cs_timings *timings);
|
||||
int aemif_check_cs_timings(struct aemif_cs_timings *timings);
|
||||
|
||||
#endif // __MEMORY_TI_AEMIF_H
|
||||
Loading…
Add table
Reference in a new issue