arm64: dts: mt7986: add Bananapi R3
Add support for Bananapi R3 SBC. - SD/eMMC support (switching first 4 bits of data-bus with sw6/D) - SPI-NAND/NOR support (switched CS by sw5/C) - all rj45 ports and both SFP working (eth1/lan4) - all USB-Ports + SIM-Slot tested - i2c and all uarts tested - wifi tested (with eeprom calibration data) The device can boot from all 4 storage options. Both, SPI and MMC, can be switched using hardware switches on the board, see https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Frank Wunderlich
Matthias Brugger
parent
918aed7abd
commit
8e01fb15b8
6 changed files with 630 additions and 0 deletions
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@ -8,6 +8,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
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@ -0,0 +1,29 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
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fragment@0 {
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target-path = "/soc/mmc@11230000";
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__overlay__ {
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bus-width = <8>;
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max-frequency = <200000000>;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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hs400-ds-delay = <0x14014>;
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non-removable;
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no-sd;
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no-sdio;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,55 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Authors: Daniel Golle <daniel@makrotopia.org>
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* Frank Wunderlich <frank-w@public-files.de>
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
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fragment@0 {
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target-path = "/soc/spi@1100a000";
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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spi_nand: spi_nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <10000000>;
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spi-tx-buswidth = <4>;
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spi-rx-buswidth = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "reserved";
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reg = <0x80000 0x300000>;
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};
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partition@380000 {
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label = "fip";
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reg = <0x380000 0x200000>;
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read-only;
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};
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partition@580000 {
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label = "ubi";
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reg = <0x580000 0x7a80000>;
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};
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};
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};
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};
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};
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};
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@ -0,0 +1,68 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Authors: Daniel Golle <daniel@makrotopia.org>
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* Frank Wunderlich <frank-w@public-files.de>
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
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fragment@0 {
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target-path = "/soc/spi@1100a000";
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2";
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reg = <0x0 0x20000>;
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read-only;
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};
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partition@20000 {
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label = "reserved";
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reg = <0x20000 0x20000>;
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};
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partition@40000 {
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label = "u-boot-env";
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reg = <0x40000 0x40000>;
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};
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partition@80000 {
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label = "reserved2";
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reg = <0x80000 0x80000>;
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};
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partition@100000 {
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label = "fip";
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reg = <0x100000 0x80000>;
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read-only;
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};
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partition@180000 {
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label = "recovery";
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reg = <0x180000 0xa80000>;
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};
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partition@c00000 {
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label = "fit";
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reg = <0xc00000 0x1400000>;
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};
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};
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};
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};
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};
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};
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23
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
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23
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
Normal file
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
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fragment@0 {
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target-path = "/soc/mmc@11230000";
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__overlay__ {
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bus-width = <4>;
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max-frequency = <52000000>;
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cap-sd-highspeed;
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status = "okay";
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};
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};
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};
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450
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
Normal file
450
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
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@ -0,0 +1,450 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Authors: Sam.Shih <sam.shih@mediatek.com>
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* Frank Wunderlich <frank-w@public-files.de>
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* Daniel Golle <daniel@makrotopia.org>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include "mt7986a.dtsi"
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/ {
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model = "Bananapi BPI-R3";
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compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
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aliases {
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serial0 = &uart0;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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dcin: regulator-12vd {
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compatible = "regulator-fixed";
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regulator-name = "12vd";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset-key {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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wps-key {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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};
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/* i2c of the left SFP cage (wan) */
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i2c_sfp1: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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/* i2c of the right SFP cage (lan) */
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i2c_sfp2: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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leds {
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compatible = "gpio-leds";
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green_led: led-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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blue_led: led-1 {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "1.8vd";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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vin-supply = <&dcin>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3.3vd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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vin-supply = <&dcin>;
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};
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/* left SFP cage (wan) */
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sfp1: sfp-1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp1>;
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los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
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tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
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tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
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};
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/* right SFP cage (lan) */
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sfp2: sfp-2 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp2>;
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los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
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tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
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tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
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};
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};
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&crypto {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "2500base-x";
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sfp = <&sfp1>;
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managed = "in-band-status";
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&mdio {
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switch: switch@31 {
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compatible = "mediatek,mt7531";
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reg = <31>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
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};
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};
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&mmc0 {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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status = "okay";
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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status = "okay";
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};
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&pcie_phy {
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status = "okay";
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};
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&pio {
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i2c_pins: i2c-pins {
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mux {
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function = "i2c";
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groups = "i2c";
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};
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};
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mmc0_pins_default: mmc0-pins {
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mux {
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function = "emmc";
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groups = "emmc_51";
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};
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conf-cmd-dat {
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pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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input-enable;
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drive-strength = <4>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
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};
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conf-clk {
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pins = "EMMC_CK";
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drive-strength = <6>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
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};
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conf-ds {
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pins = "EMMC_DSL";
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
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};
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conf-rst {
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pins = "EMMC_RSTB";
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drive-strength = <4>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
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};
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};
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mmc0_pins_uhs: mmc0-uhs-pins {
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mux {
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function = "emmc";
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groups = "emmc_51";
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};
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conf-cmd-dat {
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pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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input-enable;
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drive-strength = <4>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
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};
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conf-clk {
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pins = "EMMC_CK";
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drive-strength = <6>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
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};
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conf-ds {
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pins = "EMMC_DSL";
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
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};
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conf-rst {
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pins = "EMMC_RSTB";
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drive-strength = <4>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
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};
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};
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pcie_pins: pcie-pins {
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mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_clk", "pcie_pereset";
|
||||
};
|
||||
};
|
||||
|
||||
spi_flash_pins: spi-flash-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
};
|
||||
|
||||
spic_pins: spic-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi1_0";
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: uart1-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart1_rx_tx";
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart2_0_rx_tx";
|
||||
};
|
||||
};
|
||||
|
||||
wf_2g_5g_pins: wf-2g-5g-pins {
|
||||
mux {
|
||||
function = "wifi";
|
||||
groups = "wf_2g", "wf_5g";
|
||||
};
|
||||
conf {
|
||||
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
|
||||
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
|
||||
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
|
||||
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
|
||||
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
|
||||
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
|
||||
"WF1_TOP_CLK", "WF1_TOP_DATA";
|
||||
drive-strength = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
wf_dbdc_pins: wf-dbdc-pins {
|
||||
mux {
|
||||
function = "wifi";
|
||||
groups = "wf_dbdc";
|
||||
};
|
||||
conf {
|
||||
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
|
||||
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
|
||||
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
|
||||
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
|
||||
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
|
||||
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
|
||||
"WF1_TOP_CLK", "WF1_TOP_DATA";
|
||||
drive-strength = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
wf_led_pins: wf-led-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "wifi_led";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spic_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&switch {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port5: port@5 {
|
||||
reg = <5>;
|
||||
label = "lan4";
|
||||
phy-mode = "2500base-x";
|
||||
sfp = <&sfp2>;
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&trng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "dbdc";
|
||||
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
|
||||
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
|
||||
};
|
||||
|
||||
Loading…
Add table
Reference in a new issue