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drm/msm/dpu: Add MISR register support for interface

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Add support for setting MISR registers within the interface

Changes since V1:
- Replaced dpu_hw_intf collect_misr and setup_misr implementations with
  calls to dpu_hw_utils helper methods

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490730/
Link: https://lore.kernel.org/r/20220622171835.7558-4-quic_jesszhan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Jessica Zhang 2022-06-22 10:18:34 -07:00 • committed by Dmitry Baryshkov
parent 7b37523fb1
commit 91143873a0
2 changed files with 25 additions and 2 deletions
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19
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
View file

@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/ */
#include "dpu_hwio.h" #include "dpu_hwio.h"
@ -67,6 +69,9 @@
#define INTF_CFG2_DATABUS_WIDEN BIT(0) #define INTF_CFG2_DATABUS_WIDEN BIT(0)
#define INTF_CFG2_DATA_HCTL_EN BIT(4) #define INTF_CFG2_DATA_HCTL_EN BIT(4)
#define INTF_MISR_CTRL 0x180
#define INTF_MISR_SIGNATURE 0x184
static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
const struct dpu_mdss_cfg *m, const struct dpu_mdss_cfg *m,
void __iomem *addr, void __iomem *addr,
@ -318,6 +323,16 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
return DPU_REG_READ(c, INTF_LINE_COUNT); return DPU_REG_READ(c, INTF_LINE_COUNT);
} }
static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)
{
dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count);
}
static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)
{
return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value);
}
static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
unsigned long cap) unsigned long cap)
{ {
@ -328,6 +343,8 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
ops->get_line_count = dpu_hw_intf_get_line_count; ops->get_line_count = dpu_hw_intf_get_line_count;
if (cap & BIT(DPU_INTF_INPUT_CTRL)) if (cap & BIT(DPU_INTF_INPUT_CTRL))
ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
ops->setup_misr = dpu_hw_intf_setup_misr;
ops->collect_misr = dpu_hw_intf_collect_misr;
} }
struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,

8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
View file

@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/ */
#ifndef _DPU_HW_INTF_H #ifndef _DPU_HW_INTF_H
@ -57,6 +59,8 @@ struct intf_status {
* @ get_line_count: reads current vertical line counter * @ get_line_count: reads current vertical line counter
* @bind_pingpong_blk: enable/disable the connection with pingpong which will * @bind_pingpong_blk: enable/disable the connection with pingpong which will
* feed pixels to this interface * feed pixels to this interface
* @setup_misr: enable/disable MISR
* @collect_misr: read MISR signature
*/ */
struct dpu_hw_intf_ops { struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf, void (*setup_timing_gen)(struct dpu_hw_intf *intf,
@ -77,6 +81,8 @@ struct dpu_hw_intf_ops {
void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
bool enable, bool enable,
const enum dpu_pingpong pp); const enum dpu_pingpong pp);
void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
}; };
struct dpu_hw_intf { struct dpu_hw_intf {