drm/imagination: Implement MIPS firmware processor and MMU support
Add support for the MIPS firmware processor, used in the Series AXE GPU. The MIPS firmware processor uses a separate MMU to the rest of the GPU, so this patch adds support for that as well. Changes since v8: - Corrected license identifiers Changes since v6: - Fix integer overflow in VM map error path Changes since v5: - Use alloc_page() when allocating MIPS pagetable Changes since v3: - Get regs resource (removed from GPU resources commit) Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Donald Robson <donald.robson@imgtec.com> Link: https://lore.kernel.org/r/a114f7b3e97cb07460c7f2842901716a9207b0c4.1700668843.git.donald.robson@imgtec.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
This commit is contained in:
Sarah Walker
Maxime Ripard
parent
cc1aeedb98
commit
927f3e0253
8 changed files with 572 additions and 2 deletions
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@ -10,11 +10,13 @@ powervr-y := \
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pvr_drv.o \
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pvr_fw.o \
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pvr_fw_meta.o \
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pvr_fw_mips.o \
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pvr_fw_startstop.o \
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pvr_fw_trace.o \
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pvr_gem.o \
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pvr_mmu.o \
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pvr_power.o \
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pvr_vm.o
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pvr_vm.o \
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pvr_vm_mips.o
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obj-$(CONFIG_DRM_POWERVR) += powervr.o
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@ -50,16 +50,19 @@ pvr_device_reg_init(struct pvr_device *pvr_dev)
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{
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struct drm_device *drm_dev = from_pvr_device(pvr_dev);
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struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
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struct resource *regs_resource;
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void __iomem *regs;
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pvr_dev->regs_resource = NULL;
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pvr_dev->regs = NULL;
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regs = devm_platform_ioremap_resource(plat_dev, 0);
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regs = devm_platform_get_and_ioremap_resource(plat_dev, 0, ®s_resource);
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if (IS_ERR(regs))
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return dev_err_probe(drm_dev->dev, PTR_ERR(regs),
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"failed to ioremap gpu registers\n");
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pvr_dev->regs = regs;
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pvr_dev->regs_resource = regs_resource;
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return 0;
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}
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@ -93,6 +93,9 @@ struct pvr_device {
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/** @fw_version: Firmware version detected at runtime. */
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struct pvr_fw_version fw_version;
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/** @regs_resource: Resource representing device control registers. */
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struct resource *regs_resource;
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/**
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* @regs: Device control registers.
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*
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@ -933,6 +933,8 @@ pvr_fw_init(struct pvr_device *pvr_dev)
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if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_META)
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fw_dev->defs = &pvr_fw_defs_meta;
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else if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_MIPS)
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fw_dev->defs = &pvr_fw_defs_mips;
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else
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return -EINVAL;
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252
drivers/gpu/drm/imagination/pvr_fw_mips.c
Normal file
252
drivers/gpu/drm/imagination/pvr_fw_mips.c
Normal file
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@ -0,0 +1,252 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#include "pvr_device.h"
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#include "pvr_fw.h"
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#include "pvr_fw_mips.h"
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#include "pvr_gem.h"
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#include "pvr_rogue_mips.h"
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#include "pvr_vm_mips.h"
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#include <linux/elf.h>
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#include <linux/err.h>
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#include <linux/types.h>
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#define ROGUE_FW_HEAP_MIPS_BASE 0xC0000000
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#define ROGUE_FW_HEAP_MIPS_SHIFT 24 /* 16 MB */
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#define ROGUE_FW_HEAP_MIPS_RESERVED_SIZE SZ_1M
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/**
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* process_elf_command_stream() - Process ELF firmware image and populate
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* firmware sections
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* @pvr_dev: Device pointer.
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* @fw: Pointer to firmware image.
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* @fw_code_ptr: Pointer to FW code section.
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* @fw_data_ptr: Pointer to FW data section.
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* @fw_core_code_ptr: Pointer to FW coremem code section.
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* @fw_core_data_ptr: Pointer to FW coremem data section.
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*
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* Returns :
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* * 0 on success, or
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* * -EINVAL on any error in ELF command stream.
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*/
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static int
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process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr,
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u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr)
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{
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struct elf32_hdr *header = (struct elf32_hdr *)fw;
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struct elf32_phdr *program_header = (struct elf32_phdr *)(fw + header->e_phoff);
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struct drm_device *drm_dev = from_pvr_device(pvr_dev);
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u32 entry;
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int err;
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for (entry = 0; entry < header->e_phnum; entry++, program_header++) {
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void *write_addr;
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/* Only consider loadable entries in the ELF segment table */
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if (program_header->p_type != PT_LOAD)
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continue;
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err = pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr,
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program_header->p_memsz, fw_code_ptr, fw_data_ptr,
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fw_core_code_ptr, fw_core_data_ptr, &write_addr);
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if (err) {
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drm_err(drm_dev,
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"Addr 0x%x (size: %d) not found in any firmware segment",
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program_header->p_vaddr, program_header->p_memsz);
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return err;
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}
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/* Write to FW allocation only if available */
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if (write_addr) {
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memcpy(write_addr, fw + program_header->p_offset,
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program_header->p_filesz);
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memset((u8 *)write_addr + program_header->p_filesz, 0,
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program_header->p_memsz - program_header->p_filesz);
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}
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}
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return 0;
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}
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static int
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pvr_mips_init(struct pvr_device *pvr_dev)
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{
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pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_MIPS_SHIFT, ROGUE_FW_HEAP_MIPS_RESERVED_SIZE);
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return pvr_vm_mips_init(pvr_dev);
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}
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static void
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pvr_mips_fini(struct pvr_device *pvr_dev)
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{
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pvr_vm_mips_fini(pvr_dev);
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}
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static int
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pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
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u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr,
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u32 core_code_alloc_size)
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{
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struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
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struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
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const struct pvr_fw_layout_entry *boot_code_entry;
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const struct pvr_fw_layout_entry *boot_data_entry;
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const struct pvr_fw_layout_entry *exception_code_entry;
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const struct pvr_fw_layout_entry *stack_entry;
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struct rogue_mipsfw_boot_data *boot_data;
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dma_addr_t dma_addr;
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u32 page_nr;
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int err;
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err = process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, fw_core_code_ptr,
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fw_core_data_ptr);
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if (err)
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return err;
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boot_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_CODE);
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boot_data_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_DATA);
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exception_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_EXCEPTIONS_CODE);
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if (!boot_code_entry || !boot_data_entry || !exception_code_entry)
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return -EINVAL;
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WARN_ON(pvr_gem_get_dma_addr(fw_dev->mem.code_obj->gem, boot_code_entry->alloc_offset,
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&mips_data->boot_code_dma_addr));
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WARN_ON(pvr_gem_get_dma_addr(fw_dev->mem.data_obj->gem, boot_data_entry->alloc_offset,
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&mips_data->boot_data_dma_addr));
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WARN_ON(pvr_gem_get_dma_addr(fw_dev->mem.code_obj->gem,
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exception_code_entry->alloc_offset,
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&mips_data->exception_code_dma_addr));
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stack_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_STACK);
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if (!stack_entry)
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return -EINVAL;
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boot_data = (struct rogue_mipsfw_boot_data *)(fw_data_ptr + boot_data_entry->alloc_offset +
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ROGUE_MIPSFW_BOOTLDR_CONF_OFFSET);
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WARN_ON(pvr_fw_object_get_dma_addr(fw_dev->mem.data_obj, stack_entry->alloc_offset,
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&dma_addr));
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boot_data->stack_phys_addr = dma_addr;
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boot_data->reg_base = pvr_dev->regs_resource->start;
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for (page_nr = 0; page_nr < ARRAY_SIZE(boot_data->pt_phys_addr); page_nr++) {
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/* Firmware expects 4k pages, but host page size might be different. */
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u32 src_page_nr = (page_nr * ROGUE_MIPSFW_PAGE_SIZE_4K) >> PAGE_SHIFT;
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u32 page_offset = (page_nr * ROGUE_MIPSFW_PAGE_SIZE_4K) & ~PAGE_MASK;
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boot_data->pt_phys_addr[page_nr] = mips_data->pt_dma_addr[src_page_nr] +
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page_offset;
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}
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boot_data->pt_log2_page_size = ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
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boot_data->pt_num_pages = ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES;
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boot_data->reserved1 = 0;
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boot_data->reserved2 = 0;
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return 0;
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}
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static int
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pvr_mips_wrapper_init(struct pvr_device *pvr_dev)
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{
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struct pvr_fw_mips_data *mips_data = pvr_dev->fw_dev.processor_data.mips_data;
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const u64 remap_settings = ROGUE_MIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE;
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u32 phys_bus_width;
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int err = PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width);
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if (WARN_ON(err))
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return err;
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/* Currently MIPS FW only supported with physical bus width > 32 bits. */
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if (WARN_ON(phys_bus_width <= 32))
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return -EINVAL;
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pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_CONFIG,
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(ROGUE_MIPSFW_REGISTERS_VIRTUAL_BASE >>
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ROGUE_MIPSFW_WRAPPER_CONFIG_REGBANK_ADDR_ALIGN) |
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ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MICROMIPS);
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/* Configure remap for boot code, boot data and exceptions code areas. */
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1,
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ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN |
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ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_EN);
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2,
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(mips_data->boot_code_dma_addr &
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~ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_CLRMSK) | remap_settings);
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if (PVR_HAS_QUIRK(pvr_dev, 63553)) {
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/*
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* WA always required on 36 bit cores, to avoid continuous unmapped memory accesses
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* to address 0x0.
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*/
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WARN_ON(phys_bus_width != 36);
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1,
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ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_EN);
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2,
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(mips_data->boot_code_dma_addr &
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~ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_CLRMSK) |
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remap_settings);
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}
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1,
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ROGUE_MIPSFW_DATA_REMAP_PHYS_ADDR_IN |
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ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_EN);
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2,
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(mips_data->boot_data_dma_addr &
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~ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_CLRMSK) | remap_settings);
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1,
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ROGUE_MIPSFW_CODE_REMAP_PHYS_ADDR_IN |
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ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_EN);
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pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2,
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(mips_data->exception_code_dma_addr &
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~ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_CLRMSK) | remap_settings);
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/* Garten IDLE bit controlled by MIPS. */
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pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG,
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ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META);
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/* Turn on the EJTAG probe. */
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pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_DEBUG_CONFIG, 0);
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return 0;
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}
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static u32
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pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
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{
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struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev);
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/* MIPS cacheability is determined by page table. */
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return ((fw_obj->fw_addr_offset + offset) & pvr_dev->fw_dev.fw_heap_info.offset_mask) |
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ROGUE_FW_HEAP_MIPS_BASE;
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}
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static bool
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pvr_mips_has_fixed_data_addr(void)
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{
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return true;
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}
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const struct pvr_fw_defs pvr_fw_defs_mips = {
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.init = pvr_mips_init,
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.fini = pvr_mips_fini,
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.fw_process = pvr_mips_fw_process,
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.vm_map = pvr_vm_mips_map,
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.vm_unmap = pvr_vm_mips_unmap,
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.get_fw_addr_with_offset = pvr_mips_get_fw_addr_with_offset,
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.wrapper_init = pvr_mips_wrapper_init,
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.has_fixed_data_addr = pvr_mips_has_fixed_data_addr,
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.irq = {
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.enable_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE,
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.status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS,
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.clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR,
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.event_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN,
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.clear_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN,
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},
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};
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48
drivers/gpu/drm/imagination/pvr_fw_mips.h
Normal file
48
drivers/gpu/drm/imagination/pvr_fw_mips.h
Normal file
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@ -0,0 +1,48 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_FW_MIPS_H
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#define PVR_FW_MIPS_H
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#include "pvr_rogue_mips.h"
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#include <asm/page.h>
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#include <linux/types.h>
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/* Forward declaration from pvr_gem.h. */
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struct pvr_gem_object;
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#define PVR_MIPS_PT_PAGE_COUNT ((ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * ROGUE_MIPSFW_PAGE_SIZE_4K) \
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>> PAGE_SHIFT)
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/**
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* struct pvr_fw_mips_data - MIPS-specific data
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*/
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struct pvr_fw_mips_data {
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/**
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* @pt_pages: Pages containing MIPS pagetable.
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*/
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struct page *pt_pages[PVR_MIPS_PT_PAGE_COUNT];
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/** @pt: Pointer to CPU mapping of MIPS pagetable. */
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u32 *pt;
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/** @pt_dma_addr: DMA mappings of MIPS pagetable. */
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dma_addr_t pt_dma_addr[PVR_MIPS_PT_PAGE_COUNT];
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/** @boot_code_dma_addr: DMA address of MIPS boot code. */
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dma_addr_t boot_code_dma_addr;
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/** @boot_data_dma_addr: DMA address of MIPS boot data. */
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dma_addr_t boot_data_dma_addr;
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/** @exception_code_dma_addr: DMA address of MIPS exception code. */
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dma_addr_t exception_code_dma_addr;
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/** @cache_policy: Cache policy for this processor. */
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u32 cache_policy;
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/** @pfn_mask: PFN mask for MIPS pagetable. */
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u32 pfn_mask;
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};
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#endif /* PVR_FW_MIPS_H */
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238
drivers/gpu/drm/imagination/pvr_vm_mips.c
Normal file
238
drivers/gpu/drm/imagination/pvr_vm_mips.c
Normal file
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@ -0,0 +1,238 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#include "pvr_device.h"
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#include "pvr_fw_mips.h"
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#include "pvr_gem.h"
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#include "pvr_mmu.h"
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#include "pvr_rogue_mips.h"
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#include "pvr_vm.h"
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||||
#include "pvr_vm_mips.h"
|
||||
|
||||
#include <drm/drm_managed.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* pvr_vm_mips_init() - Initialise MIPS FW pagetable
|
||||
* @pvr_dev: Target PowerVR device.
|
||||
*
|
||||
* Returns:
|
||||
* * 0 on success,
|
||||
* * -%EINVAL,
|
||||
* * Any error returned by pvr_gem_object_create(), or
|
||||
* * And error returned by pvr_gem_object_vmap().
|
||||
*/
|
||||
int
|
||||
pvr_vm_mips_init(struct pvr_device *pvr_dev)
|
||||
{
|
||||
u32 pt_size = 1 << ROGUE_MIPSFW_LOG2_PAGETABLE_SIZE_4K(pvr_dev);
|
||||
struct device *dev = from_pvr_device(pvr_dev)->dev;
|
||||
struct pvr_fw_mips_data *mips_data;
|
||||
u32 phys_bus_width;
|
||||
int page_nr;
|
||||
int err;
|
||||
|
||||
/* Page table size must be at most ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * 4k pages. */
|
||||
if (pt_size > ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * SZ_4K)
|
||||
return -EINVAL;
|
||||
|
||||
if (PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width))
|
||||
return -EINVAL;
|
||||
|
||||
mips_data = drmm_kzalloc(from_pvr_device(pvr_dev), sizeof(*mips_data), GFP_KERNEL);
|
||||
if (!mips_data)
|
||||
return -ENOMEM;
|
||||
|
||||
for (page_nr = 0; page_nr < ARRAY_SIZE(mips_data->pt_pages); page_nr++) {
|
||||
mips_data->pt_pages[page_nr] = alloc_page(GFP_KERNEL | __GFP_ZERO);
|
||||
if (!mips_data->pt_pages[page_nr]) {
|
||||
err = -ENOMEM;
|
||||
goto err_free_pages;
|
||||
}
|
||||
|
||||
mips_data->pt_dma_addr[page_nr] = dma_map_page(dev, mips_data->pt_pages[page_nr], 0,
|
||||
PAGE_SIZE, DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(dev, mips_data->pt_dma_addr[page_nr])) {
|
||||
err = -ENOMEM;
|
||||
goto err_free_pages;
|
||||
}
|
||||
}
|
||||
|
||||
mips_data->pt = vmap(mips_data->pt_pages, pt_size >> PAGE_SHIFT, VM_MAP,
|
||||
pgprot_writecombine(PAGE_KERNEL));
|
||||
if (!mips_data->pt) {
|
||||
err = -ENOMEM;
|
||||
goto err_free_pages;
|
||||
}
|
||||
|
||||
mips_data->pfn_mask = (phys_bus_width > 32) ? ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT :
|
||||
ROGUE_MIPSFW_ENTRYLO_PFN_MASK;
|
||||
|
||||
mips_data->cache_policy = (phys_bus_width > 32) ? ROGUE_MIPSFW_CACHED_POLICY_ABOVE_32BIT :
|
||||
ROGUE_MIPSFW_CACHED_POLICY;
|
||||
|
||||
pvr_dev->fw_dev.processor_data.mips_data = mips_data;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_pages:
|
||||
for (; page_nr >= 0; page_nr--) {
|
||||
if (mips_data->pt_dma_addr[page_nr])
|
||||
dma_unmap_page(from_pvr_device(pvr_dev)->dev,
|
||||
mips_data->pt_dma_addr[page_nr], PAGE_SIZE, DMA_TO_DEVICE);
|
||||
|
||||
if (mips_data->pt_pages[page_nr])
|
||||
__free_page(mips_data->pt_pages[page_nr]);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* pvr_vm_mips_fini() - Release MIPS FW pagetable
|
||||
* @pvr_dev: Target PowerVR device.
|
||||
*/
|
||||
void
|
||||
pvr_vm_mips_fini(struct pvr_device *pvr_dev)
|
||||
{
|
||||
struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
|
||||
struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
|
||||
int page_nr;
|
||||
|
||||
vunmap(mips_data->pt);
|
||||
for (page_nr = ARRAY_SIZE(mips_data->pt_pages) - 1; page_nr >= 0; page_nr--) {
|
||||
dma_unmap_page(from_pvr_device(pvr_dev)->dev,
|
||||
mips_data->pt_dma_addr[page_nr], PAGE_SIZE, DMA_TO_DEVICE);
|
||||
|
||||
__free_page(mips_data->pt_pages[page_nr]);
|
||||
}
|
||||
|
||||
fw_dev->processor_data.mips_data = NULL;
|
||||
}
|
||||
|
||||
static u32
|
||||
get_mips_pte_flags(bool read, bool write, u32 cache_policy)
|
||||
{
|
||||
u32 flags = 0;
|
||||
|
||||
if (read && write) /* Read/write. */
|
||||
flags |= ROGUE_MIPSFW_ENTRYLO_DIRTY_EN;
|
||||
else if (write) /* Write only. */
|
||||
flags |= ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_EN;
|
||||
else
|
||||
WARN_ON(!read);
|
||||
|
||||
flags |= cache_policy << ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT;
|
||||
|
||||
flags |= ROGUE_MIPSFW_ENTRYLO_VALID_EN | ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN;
|
||||
|
||||
return flags;
|
||||
}
|
||||
|
||||
/**
|
||||
* pvr_vm_mips_map() - Map a FW object into MIPS address space
|
||||
* @pvr_dev: Target PowerVR device.
|
||||
* @fw_obj: FW object to map.
|
||||
*
|
||||
* Returns:
|
||||
* * 0 on success,
|
||||
* * -%EINVAL if object does not reside within FW address space, or
|
||||
* * Any error returned by pvr_fw_object_get_dma_addr().
|
||||
*/
|
||||
int
|
||||
pvr_vm_mips_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
|
||||
{
|
||||
struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
|
||||
struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
|
||||
struct pvr_gem_object *pvr_obj = fw_obj->gem;
|
||||
const u64 start = fw_obj->fw_mm_node.start;
|
||||
const u64 size = fw_obj->fw_mm_node.size;
|
||||
u64 end;
|
||||
u32 cache_policy;
|
||||
u32 pte_flags;
|
||||
u32 start_pfn;
|
||||
u32 end_pfn;
|
||||
s32 pfn;
|
||||
int err;
|
||||
|
||||
if (check_add_overflow(start, size - 1, &end))
|
||||
return -EINVAL;
|
||||
|
||||
if (start < ROGUE_FW_HEAP_BASE ||
|
||||
start >= ROGUE_FW_HEAP_BASE + fw_dev->fw_heap_info.raw_size ||
|
||||
end < ROGUE_FW_HEAP_BASE ||
|
||||
end >= ROGUE_FW_HEAP_BASE + fw_dev->fw_heap_info.raw_size ||
|
||||
(start & ROGUE_MIPSFW_PAGE_MASK_4K) ||
|
||||
((end + 1) & ROGUE_MIPSFW_PAGE_MASK_4K))
|
||||
return -EINVAL;
|
||||
|
||||
start_pfn = (start & fw_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
|
||||
end_pfn = (end & fw_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
|
||||
|
||||
if (pvr_obj->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
|
||||
cache_policy = ROGUE_MIPSFW_UNCACHED_CACHE_POLICY;
|
||||
else
|
||||
cache_policy = mips_data->cache_policy;
|
||||
|
||||
pte_flags = get_mips_pte_flags(true, true, cache_policy);
|
||||
|
||||
for (pfn = start_pfn; pfn <= end_pfn; pfn++) {
|
||||
dma_addr_t dma_addr;
|
||||
u32 pte;
|
||||
|
||||
err = pvr_fw_object_get_dma_addr(fw_obj,
|
||||
(pfn - start_pfn) <<
|
||||
ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K,
|
||||
&dma_addr);
|
||||
if (err)
|
||||
goto err_unmap_pages;
|
||||
|
||||
pte = ((dma_addr >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
|
||||
<< ROGUE_MIPSFW_ENTRYLO_PFN_SHIFT) & mips_data->pfn_mask;
|
||||
pte |= pte_flags;
|
||||
|
||||
WRITE_ONCE(mips_data->pt[pfn], pte);
|
||||
}
|
||||
|
||||
pvr_mmu_flush_request_all(pvr_dev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_unmap_pages:
|
||||
for (; pfn >= start_pfn; pfn--)
|
||||
WRITE_ONCE(mips_data->pt[pfn], 0);
|
||||
|
||||
pvr_mmu_flush_request_all(pvr_dev);
|
||||
WARN_ON(pvr_mmu_flush_exec(pvr_dev, true));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* pvr_vm_mips_unmap() - Unmap a FW object into MIPS address space
|
||||
* @pvr_dev: Target PowerVR device.
|
||||
* @fw_obj: FW object to unmap.
|
||||
*/
|
||||
void
|
||||
pvr_vm_mips_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
|
||||
{
|
||||
struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
|
||||
struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
|
||||
const u64 start = fw_obj->fw_mm_node.start;
|
||||
const u64 size = fw_obj->fw_mm_node.size;
|
||||
const u64 end = start + size;
|
||||
|
||||
const u32 start_pfn = (start & fw_dev->fw_heap_info.offset_mask) >>
|
||||
ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
|
||||
const u32 end_pfn = (end & fw_dev->fw_heap_info.offset_mask) >>
|
||||
ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
|
||||
|
||||
for (u32 pfn = start_pfn; pfn < end_pfn; pfn++)
|
||||
WRITE_ONCE(mips_data->pt[pfn], 0);
|
||||
|
||||
pvr_mmu_flush_request_all(pvr_dev);
|
||||
WARN_ON(pvr_mmu_flush_exec(pvr_dev, true));
|
||||
}
|
||||
22
drivers/gpu/drm/imagination/pvr_vm_mips.h
Normal file
22
drivers/gpu/drm/imagination/pvr_vm_mips.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
||||
/* Copyright (c) 2023 Imagination Technologies Ltd. */
|
||||
|
||||
#ifndef PVR_VM_MIPS_H
|
||||
#define PVR_VM_MIPS_H
|
||||
|
||||
/* Forward declaration from pvr_device.h. */
|
||||
struct pvr_device;
|
||||
|
||||
/* Forward declaration from pvr_gem.h. */
|
||||
struct pvr_fw_object;
|
||||
|
||||
int
|
||||
pvr_vm_mips_init(struct pvr_device *pvr_dev);
|
||||
void
|
||||
pvr_vm_mips_fini(struct pvr_device *pvr_dev);
|
||||
int
|
||||
pvr_vm_mips_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj);
|
||||
void
|
||||
pvr_vm_mips_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj);
|
||||
|
||||
#endif /* PVR_VM_MIPS_H */
|
||||
Loading…
Add table
Reference in a new issue