drm/amdgpu: add sysfs node for compute partition mode
Add current/available compute partitin mode sysfs node. v2: make the sysfs node as IP independent one in amdgpu_gfx.c Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Le Ma
Alex Deucher
parent
3566938b34
commit
98a54e88e8
6 changed files with 241 additions and 0 deletions
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@ -3634,6 +3634,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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mutex_init(&adev->srbm_mutex);
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mutex_init(&adev->gfx.pipe_reserve_mutex);
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mutex_init(&adev->gfx.gfx_off_mutex);
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mutex_init(&adev->gfx.partition_mutex);
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mutex_init(&adev->grbm_idx_mutex);
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mutex_init(&adev->mn_lock);
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mutex_init(&adev->virt.vf_errors.lock);
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@ -1174,3 +1174,135 @@ bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
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return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
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adev->gfx.num_xcc_per_xcp : 1));
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}
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static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
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struct device_attribute *addr,
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char *buf)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = drm_to_adev(ddev);
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enum amdgpu_gfx_partition mode;
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char *partition_mode;
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mode = adev->gfx.funcs->query_partition_mode(adev);
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switch (mode) {
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case AMDGPU_SPX_PARTITION_MODE:
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partition_mode = "SPX";
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break;
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case AMDGPU_DPX_PARTITION_MODE:
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partition_mode = "DPX";
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break;
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case AMDGPU_TPX_PARTITION_MODE:
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partition_mode = "TPX";
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break;
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case AMDGPU_QPX_PARTITION_MODE:
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partition_mode = "QPX";
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break;
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case AMDGPU_CPX_PARTITION_MODE:
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partition_mode = "CPX";
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break;
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default:
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partition_mode = "UNKNOWN";
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break;
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}
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return sysfs_emit(buf, "%s\n", partition_mode);
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}
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static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
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struct device_attribute *addr,
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const char *buf, size_t count)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = drm_to_adev(ddev);
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enum amdgpu_gfx_partition mode;
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int ret;
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if (adev->gfx.num_xcd % 2 != 0)
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return -EINVAL;
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if (!strncasecmp("SPX", buf, strlen("SPX"))) {
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mode = AMDGPU_SPX_PARTITION_MODE;
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} else if (!strncasecmp("DPX", buf, strlen("DPX"))) {
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if (adev->gfx.num_xcd != 4 || adev->gfx.num_xcd != 8)
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return -EINVAL;
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mode = AMDGPU_DPX_PARTITION_MODE;
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} else if (!strncasecmp("TPX", buf, strlen("TPX"))) {
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if (adev->gfx.num_xcd != 6)
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return -EINVAL;
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mode = AMDGPU_TPX_PARTITION_MODE;
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} else if (!strncasecmp("QPX", buf, strlen("QPX"))) {
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if (adev->gfx.num_xcd != 8)
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return -EINVAL;
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mode = AMDGPU_QPX_PARTITION_MODE;
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} else if (!strncasecmp("CPX", buf, strlen("CPX"))) {
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mode = AMDGPU_CPX_PARTITION_MODE;
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} else {
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return -EINVAL;
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}
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mutex_lock(&adev->gfx.partition_mutex);
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ret = adev->gfx.funcs->switch_partition_mode(adev, mode);
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mutex_unlock(&adev->gfx.partition_mutex);
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if (ret)
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return ret;
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return count;
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}
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static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
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struct device_attribute *addr,
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char *buf)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = drm_to_adev(ddev);
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char *supported_partition;
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/* TBD */
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switch (adev->gfx.num_xcd) {
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case 8:
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supported_partition = "SPX, DPX, QPX, CPX";
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break;
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case 6:
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supported_partition = "SPX, TPX, CPX";
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break;
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case 4:
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supported_partition = "SPX, DPX, CPX";
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break;
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/* this seems only existing in emulation phase */
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case 2:
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supported_partition = "SPX, CPX";
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break;
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default:
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supported_partition = "Not supported";
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break;
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}
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return sysfs_emit(buf, "%s\n", supported_partition);
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}
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static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
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amdgpu_gfx_get_current_compute_partition,
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amdgpu_gfx_set_compute_partition);
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static DEVICE_ATTR(available_compute_partition, S_IRUGO,
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amdgpu_gfx_get_available_compute_partition, NULL);
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int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
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{
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int r;
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r = device_create_file(adev->dev, &dev_attr_current_compute_partition);
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if (r)
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return r;
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r = device_create_file(adev->dev, &dev_attr_available_compute_partition);
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if (r)
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return r;
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return 0;
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}
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@ -259,6 +259,10 @@ struct amdgpu_gfx_funcs {
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void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
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int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
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struct amdgpu_gfx_shadow_info *shadow_info);
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enum amdgpu_gfx_partition
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(*query_partition_mode)(struct amdgpu_device *adev);
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int (*switch_partition_mode)(struct amdgpu_device *adev,
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enum amdgpu_gfx_partition mode);
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};
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struct sq_work {
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@ -394,6 +398,7 @@ struct amdgpu_gfx {
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enum amdgpu_gfx_partition partition_mode;
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uint32_t num_xcd;
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uint32_t num_xcc_per_xcp;
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struct mutex partition_mutex;
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};
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#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
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@ -478,4 +483,5 @@ int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry);
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bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev);
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#endif
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@ -95,6 +95,9 @@ struct amdgpu_nbio_funcs {
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void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev);
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void (*clear_doorbell_interrupt)(struct amdgpu_device *adev);
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u32 (*get_rom_offset)(struct amdgpu_device *adev);
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u32 (*get_compute_partition_mode)(struct amdgpu_device *adev);
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void (*set_compute_partition_mode)(struct amdgpu_device *adev,
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enum amdgpu_gfx_partition mode);
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};
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struct amdgpu_nbio {
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@ -662,6 +662,67 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
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soc15_grbm_select(adev, me, pipe, q, vm, 0);
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}
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static enum amdgpu_gfx_partition
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gfx_v9_4_3_query_compute_partition(struct amdgpu_device *adev)
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{
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enum amdgpu_gfx_partition mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;
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if (adev->nbio.funcs->get_compute_partition_mode)
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mode = adev->nbio.funcs->get_compute_partition_mode(adev);
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return mode;
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}
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static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
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enum amdgpu_gfx_partition mode)
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{
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u32 tmp = 0;
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int num_xcc_per_partition, i;
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if (mode == adev->gfx.partition_mode)
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return mode;
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switch (mode) {
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case AMDGPU_SPX_PARTITION_MODE:
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num_xcc_per_partition = adev->gfx.num_xcd;
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break;
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case AMDGPU_DPX_PARTITION_MODE:
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num_xcc_per_partition = adev->gfx.num_xcd / 2;
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break;
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case AMDGPU_TPX_PARTITION_MODE:
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num_xcc_per_partition = adev->gfx.num_xcd / 3;
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break;
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case AMDGPU_QPX_PARTITION_MODE:
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num_xcc_per_partition = adev->gfx.num_xcd / 4;
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break;
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case AMDGPU_CPX_PARTITION_MODE:
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num_xcc_per_partition = 1;
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break;
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default:
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return -EINVAL;
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}
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/* TODO:
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* Stop user queues and threads, and make sure GPU is empty of work.
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*/
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for (i = 0; i < adev->gfx.num_xcd; i++) {
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tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
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num_xcc_per_partition);
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tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
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i % num_xcc_per_partition);
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WREG32_SOC15(GC, i, regCP_HYP_XCP_CTL, tmp);
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}
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if (adev->nbio.funcs->set_compute_partition_mode)
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adev->nbio.funcs->set_compute_partition_mode(adev, mode);
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adev->gfx.num_xcc_per_xcp = num_xcc_per_partition;
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adev->gfx.partition_mode = mode;
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return 0;
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}
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static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
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.get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
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.select_se_sh = &gfx_v9_4_3_select_se_sh,
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@ -669,6 +730,8 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
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.read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
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.read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
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.select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
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.query_partition_mode = &gfx_v9_4_3_query_compute_partition,
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.switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
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};
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static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
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@ -858,6 +921,10 @@ static int gfx_v9_4_3_sw_init(void *handle)
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if (r)
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return r;
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r = amdgpu_gfx_sysfs_init(adev);
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if (r)
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return r;
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return 0;
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}
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@ -347,6 +347,36 @@ static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
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DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
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}
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static enum amdgpu_gfx_partition nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
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{
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u32 tmp;
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tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_CAP);
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if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, SPX_SUPPORT))
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return AMDGPU_SPX_PARTITION_MODE;
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else if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, DPX_SUPPORT))
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return AMDGPU_DPX_PARTITION_MODE;
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else if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, TPX_SUPPORT))
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return AMDGPU_TPX_PARTITION_MODE;
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else if (REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_CAP, CPX_SUPPORT))
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return AMDGPU_CPX_PARTITION_MODE;
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else
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return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;
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}
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static void nbio_v7_9_set_compute_partition_mode(struct amdgpu_device *adev,
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enum amdgpu_gfx_partition mode)
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{
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u32 tmp;
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tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_CAP);
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tmp &= ~0x1f;
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tmp |= 1 << mode;
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_CAP, tmp);
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}
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const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
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.get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
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.get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
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@ -366,4 +396,6 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
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.get_clockgating_state = nbio_v7_9_get_clockgating_state,
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.ih_control = nbio_v7_9_ih_control,
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.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
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.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
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.set_compute_partition_mode = nbio_v7_9_set_compute_partition_mode,
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};
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