clk: Convert __clk_get_flags() to clk_hw_get_flags()
Mostly converted with the following snippet: @@ struct clk_hw *E; @@ -__clk_get_flags(E->clk) +clk_hw_get_flags(E) Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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98d8a60ecc
17 changed files with 21 additions and 21 deletions
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@ -310,7 +310,7 @@ static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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if (!mul)
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if (!mul)
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div = CDCE706_DIVIDER_DIVIDER_MAX;
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div = CDCE706_DIVIDER_DIVIDER_MAX;
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if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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unsigned long best_diff = rate;
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unsigned long best_diff = rate;
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unsigned long best_div = 0;
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unsigned long best_div = 0;
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struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
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struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
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@ -78,7 +78,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
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mux_hw && mux_ops && mux_ops->set_parent) {
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mux_hw && mux_ops && mux_ops->set_parent) {
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req->best_parent_hw = NULL;
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req->best_parent_hw = NULL;
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if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
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parent = clk_get_parent(mux_hw->clk);
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parent = clk_get_parent(mux_hw->clk);
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req->best_parent_hw = __clk_get_hw(parent);
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req->best_parent_hw = __clk_get_hw(parent);
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req->best_parent_rate = __clk_get_rate(parent);
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req->best_parent_rate = __clk_get_rate(parent);
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@ -290,7 +290,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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maxdiv = _get_maxdiv(table, width, flags);
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maxdiv = _get_maxdiv(table, width, flags);
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if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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parent_rate = *best_parent_rate;
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bestdiv = _div_round(table, parent_rate, rate, flags);
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bestdiv = _div_round(table, parent_rate, rate, flags);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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@ -41,7 +41,7 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
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{
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{
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struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
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struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
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if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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unsigned long best_parent;
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unsigned long best_parent;
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best_parent = (rate / fix->mult) * fix->div;
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best_parent = (rate / fix->mult) * fix->div;
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@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
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divby4 = 1;
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divby4 = 1;
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/* multisync can set pll */
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/* multisync can set pll */
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if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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/*
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/*
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* find largest integer divider for max
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* find largest integer divider for max
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* vco frequency and given target rate
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* vco frequency and given target rate
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@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
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rate = SI5351_CLKOUT_MIN_FREQ;
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rate = SI5351_CLKOUT_MIN_FREQ;
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/* request frequency if multisync master */
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/* request frequency if multisync master */
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if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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/* use r divider for frequencies below 1MHz */
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/* use r divider for frequencies below 1MHz */
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rdiv = SI5351_OUTPUT_CLK_DIV_1;
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rdiv = SI5351_OUTPUT_CLK_DIV_1;
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while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
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while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
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@ -175,7 +175,7 @@ static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
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if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
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if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
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mult = 2;
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mult = 2;
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if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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unsigned long best_parent = rate / mult;
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unsigned long best_parent = rate / mult;
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*prate =
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*prate =
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@ -420,7 +420,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
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if (index < 0)
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if (index < 0)
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return index;
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return index;
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clk_flags = __clk_get_flags(hw->clk);
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clk_flags = clk_hw_get_flags(hw);
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p = clk_get_parent_by_index(hw->clk, index);
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p = clk_get_parent_by_index(hw->clk, index);
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if (clk_flags & CLK_SET_RATE_PARENT) {
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if (clk_flags & CLK_SET_RATE_PARENT) {
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rate = rate * f->pre_div;
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rate = rate * f->pre_div;
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@ -192,7 +192,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw,
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if (index < 0)
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if (index < 0)
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return index;
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return index;
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clk_flags = __clk_get_flags(hw->clk);
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clk_flags = clk_hw_get_flags(hw);
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p = clk_get_parent_by_index(hw->clk, index);
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p = clk_get_parent_by_index(hw->clk, index);
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if (clk_flags & CLK_SET_RATE_PARENT) {
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if (clk_flags & CLK_SET_RATE_PARENT) {
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if (f->pre_div) {
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if (f->pre_div) {
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@ -109,7 +109,7 @@ static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
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/* Round div according to exact prate and wished rate */
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/* Round div according to exact prate and wished rate */
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div = clk_best_div(*prate, rate);
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div = clk_best_div(*prate, rate);
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if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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*prate = rate * div;
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*prate = rate * div;
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return rate;
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return rate;
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}
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}
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@ -92,7 +92,7 @@ static int clk_factors_determine_rate(struct clk_hw *hw,
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parent = clk_get_parent_by_index(clk, i);
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parent = clk_get_parent_by_index(clk, i);
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if (!parent)
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if (!parent)
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continue;
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continue;
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if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
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parent_rate = __clk_round_rate(parent, req->rate);
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parent_rate = __clk_round_rate(parent, req->rate);
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else
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else
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parent_rate = __clk_get_rate(parent);
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parent_rate = __clk_get_rate(parent);
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@ -133,7 +133,7 @@ static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw,
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parent = clk_get_parent_by_index(clk, i);
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parent = clk_get_parent_by_index(clk, i);
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if (!parent)
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if (!parent)
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continue;
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continue;
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if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
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parent_rate = __clk_round_rate(parent, req->rate);
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parent_rate = __clk_round_rate(parent, req->rate);
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else
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else
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parent_rate = __clk_get_rate(parent);
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parent_rate = __clk_get_rate(parent);
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@ -339,11 +339,11 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
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if (!IS_ERR(clk)) {
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if (!IS_ERR(clk)) {
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setup->clk = clk;
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setup->clk = clk;
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if (setup->clkdm_name) {
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if (setup->clkdm_name) {
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if (__clk_get_flags(clk) & CLK_IS_BASIC) {
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clk_hw = __clk_get_hw(clk);
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if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
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pr_warn("can't setup clkdm for basic clk %s\n",
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pr_warn("can't setup clkdm for basic clk %s\n",
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setup->name);
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setup->name);
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} else {
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} else {
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clk_hw = __clk_get_hw(clk);
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to_clk_hw_omap(clk_hw)->clkdm_name =
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to_clk_hw_omap(clk_hw)->clkdm_name =
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setup->clkdm_name;
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setup->clkdm_name;
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omap2_init_clk_clkdm(clk_hw);
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omap2_init_clk_clkdm(clk_hw);
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@ -120,12 +120,12 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
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__func__, node->full_name, i, PTR_ERR(clk));
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__func__, node->full_name, i, PTR_ERR(clk));
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continue;
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continue;
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}
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}
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if (__clk_get_flags(clk) & CLK_IS_BASIC) {
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clk_hw = __clk_get_hw(clk);
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if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
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pr_warn("can't setup clkdm for basic clk %s\n",
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pr_warn("can't setup clkdm for basic clk %s\n",
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__clk_get_name(clk));
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__clk_get_name(clk));
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continue;
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continue;
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}
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}
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clk_hw = __clk_get_hw(clk);
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to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
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to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
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omap2_init_clk_clkdm(clk_hw);
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omap2_init_clk_clkdm(clk_hw);
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}
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}
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@ -155,7 +155,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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maxdiv = _get_maxdiv(divider);
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maxdiv = _get_maxdiv(divider);
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if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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parent_rate = *best_parent_rate;
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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@ -163,7 +163,7 @@ static void __init _register_dpll(struct clk_hw *hw,
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clk = clk_register(NULL, &clk_hw->hw);
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clk = clk_register(NULL, &clk_hw->hw);
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if (!IS_ERR(clk)) {
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if (!IS_ERR(clk)) {
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omap2_init_clk_hw_omap_clocks(clk);
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omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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kfree(clk_hw->hw.init->parent_names);
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kfree(clk_hw->hw.init->parent_names);
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kfree(clk_hw->hw.init);
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kfree(clk_hw->hw.init);
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@ -320,7 +320,7 @@ static void _register_dpll_x2(struct device_node *node,
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if (IS_ERR(clk)) {
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if (IS_ERR(clk)) {
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kfree(clk_hw);
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kfree(clk_hw);
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} else {
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} else {
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omap2_init_clk_hw_omap_clocks(clk);
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omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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}
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}
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}
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@ -711,7 +711,7 @@ static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
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do {
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do {
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parent = __clk_get_parent(hw->clk);
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parent = __clk_get_parent(hw->clk);
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hw = __clk_get_hw(parent);
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hw = __clk_get_hw(parent);
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} while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
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} while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
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if (!hw)
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if (!hw)
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break;
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break;
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pclk = to_clk_hw_omap(hw);
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pclk = to_clk_hw_omap(hw);
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@ -63,7 +63,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,
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if (IS_ERR(clk))
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if (IS_ERR(clk))
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kfree(clk_hw);
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kfree(clk_hw);
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else
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else
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omap2_init_clk_hw_omap_clocks(clk);
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omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
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return clk;
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return clk;
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}
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}
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