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net: enetc: optimize the allocation of tx_bdr

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There is a situation where num_tx_rings cannot be divided by bdr_int_num.
For example, num_tx_rings is 8 and bdr_int_num is 3. According to the
previous logic, this results in two tx_bdr corresponding memories not
being allocated, so when sending packets to tx ring 6 or 7, wild pointers
will be accessed. Of course, this issue doesn't exist on LS1028A, because
its num_tx_rings is 8, and bdr_int_num is either 1 or 2. However, there
is a risk for the upcoming i.MX95. Therefore, it is necessary to ensure
that each tx_bdr can be allocated to the corresponding memory.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Clark Wang 2024-10-30 17:39:21 +08:00 • committed by David S. Miller
parent b4bfd0a904
commit 9e7f211619
1 changed files with 8 additions and 2 deletions
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10
drivers/net/ethernet/freescale/enetc/enetc.c
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@ -3084,10 +3084,10 @@ static void enetc_int_vector_destroy(struct enetc_ndev_priv *priv, int i)
int enetc_alloc_msix(struct enetc_ndev_priv *priv)
{
struct pci_dev *pdev = priv->si->pdev;
int v_tx_rings, v_remainder;
int num_stack_tx_queues;
int first_xdp_tx_ring;
int i, n, err, nvec;
int v_tx_rings;
nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num;
/* allocate MSIX for both messaging and Rx/Tx interrupts */
@ -3101,9 +3101,15 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv)
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
v_remainder = priv->num_tx_rings % priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
err = enetc_int_vector_init(priv, i, v_tx_rings);
/* Distribute the remaining TX rings to the first v_remainder
* interrupt vectors
*/
int num_tx_rings = i < v_remainder ? v_tx_rings + 1 : v_tx_rings;
err = enetc_int_vector_init(priv, i, num_tx_rings);
if (err)
goto fail;
}