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LoongArch changes for v6.14

Browse source 
1, Migrate to the generic rule for built-in DTB;
 2, Disable FIX_EARLYCON_MEM when ARCH_IOREMAP is enabled;
 3, Derive timer max_delta from PRCFG1's timer_bits;
 4, Correct the cacheinfo sharing information;
 5, Add pgprot_nx() implementation;
 6, Add debugfs entries to switch SFB/TSO state;
 7, Change the maximum number of watchpoints;
 8, Some bug fixes and other small changes.
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Merge tag 'loongarch-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch updates from Huacai Chen:

 - Migrate to the generic rule for built-in DTB

 - Disable FIX_EARLYCON_MEM when ARCH_IOREMAP is enabled

 - Derive timer max_delta from PRCFG1's timer_bits

 - Correct the cacheinfo sharing information

 - Add pgprot_nx() implementation

 - Add debugfs entries to switch SFB/TSO state

 - Change the maximum number of watchpoints

 - Some bug fixes and other small changes

* tag 'loongarch-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
  LoongArch: Extend the maximum number of watchpoints
  LoongArch: Change 8 to 14 for LOONGARCH_MAX_{BRP,WRP}
  LoongArch: Add debugfs entries to switch SFB/TSO state
  LoongArch: Fix warnings during S3 suspend
  LoongArch: Adjust SETUP_SLEEP and SETUP_WAKEUP
  LoongArch: Refactor bug_handler() implementation
  LoongArch: Add pgprot_nx() implementation
  LoongArch: Correct the __switch_to() prototype in comments
  LoongArch: Correct the cacheinfo sharing information
  LoongArch: Derive timer max_delta from PRCFG1's timer_bits
  LoongArch: Disable FIX_EARLYCON_MEM when ARCH_IOREMAP is enabled
  LoongArch: Migrate to the generic rule for built-in DTB
This commit is contained in:
Linus Torvalds 2025-01-28 08:52:01 -08:00
commit 9ff28f2fad
22 changed files with 312 additions and 31 deletions
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1
arch/loongarch/Kbuild
View file

@ -4,7 +4,6 @@ obj-y += net/
obj-y += vdso/
obj-$(CONFIG_KVM) += kvm/
obj-$(CONFIG_BUILTIN_DTB) += boot/dts/
# for cleaning
subdir- += boot

3
arch/loongarch/Kconfig
View file

@ -249,7 +249,7 @@ config MACH_LOONGSON64
def_bool 64BIT
config FIX_EARLYCON_MEM
def_bool y
def_bool !ARCH_IOREMAP
config PGTABLE_2LEVEL
bool
@ -400,6 +400,7 @@ endchoice
config BUILTIN_DTB
bool "Enable built-in dtb in kernel"
depends on OF
select GENERIC_BUILTIN_DTB
help
Some existing systems do not provide a canonical device tree to
the kernel at boot time. Let's provide a device tree table in the

2
arch/loongarch/boot/dts/Makefile
View file

@ -1,5 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-y = loongson-2k0500-ref.dtb loongson-2k1000-ref.dtb loongson-2k2000-ref.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))

1
arch/loongarch/include/asm/cpu-info.h
View file

@ -57,6 +57,7 @@ struct cpuinfo_loongarch {
int global_id; /* physical global thread number */
int vabits; /* Virtual Address size in bits */
int pabits; /* Physical Address size in bits */
int timerbits; /* Width of arch timer in bits */
unsigned int ksave_mask; /* Usable KSave mask. */
unsigned int watch_dreg_count; /* Number data breakpoints */
unsigned int watch_ireg_count; /* Number instruction breakpoints */

4
arch/loongarch/include/asm/hw_breakpoint.h
View file

@ -38,8 +38,8 @@ struct arch_hw_breakpoint {
* Limits.
* Changing these will require modifications to the register accessors.
*/
#define LOONGARCH_MAX_BRP 8
#define LOONGARCH_MAX_WRP 8
#define LOONGARCH_MAX_BRP 14
#define LOONGARCH_MAX_WRP 14
/* Virtual debug register bases. */
#define CSR_CFG_ADDR 0

76
arch/loongarch/include/asm/loongarch.h
View file

@ -108,6 +108,12 @@
#define CPUCFG3_SPW_HG_HF BIT(11)
#define CPUCFG3_RVA BIT(12)
#define CPUCFG3_RVAMAX GENMASK(16, 13)
#define CPUCFG3_ALDORDER_CAP BIT(18) /* All address load ordered, capability */
#define CPUCFG3_ASTORDER_CAP BIT(19) /* All address store ordered, capability */
#define CPUCFG3_ALDORDER_STA BIT(20) /* All address load ordered, status */
#define CPUCFG3_ASTORDER_STA BIT(21) /* All address store ordered, status */
#define CPUCFG3_SLDORDER_CAP BIT(22) /* Same address load ordered, capability */
#define CPUCFG3_SLDORDER_STA BIT(23) /* Same address load ordered, status */
#define LOONGARCH_CPUCFG4 0x4
#define CPUCFG4_CCFREQ GENMASK(31, 0)
@ -466,7 +472,6 @@
#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
#define CSR_TCFG_VAL_SHIFT 2
#define CSR_TCFG_VAL_WIDTH 48
#define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
#define CSR_TCFG_PERIOD_SHIFT 1
#define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
@ -566,6 +571,15 @@
/* Implement dependent */
#define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */
#define CSR_LDSTORDER_SHIFT 28
#define CSR_LDSTORDER_WIDTH 3
#define CSR_LDSTORDER_MASK (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT)
#define CSR_LDSTORDER_NLD_NST (_ULCAST_(0x0) << CSR_LDSTORDER_SHIFT) /* 000 = No Load No Store */
#define CSR_LDSTORDER_ALD_NST (_ULCAST_(0x1) << CSR_LDSTORDER_SHIFT) /* 001 = All Load No Store */
#define CSR_LDSTORDER_SLD_NST (_ULCAST_(0x3) << CSR_LDSTORDER_SHIFT) /* 011 = Same Load No Store */
#define CSR_LDSTORDER_NLD_AST (_ULCAST_(0x4) << CSR_LDSTORDER_SHIFT) /* 100 = No Load All Store */
#define CSR_LDSTORDER_ALD_AST (_ULCAST_(0x5) << CSR_LDSTORDER_SHIFT) /* 101 = All Load All Store */
#define CSR_LDSTORDER_SLD_AST (_ULCAST_(0x7) << CSR_LDSTORDER_SHIFT) /* 111 = Same Load All Store */
#define CSR_MISPEC_SHIFT 20
#define CSR_MISPEC_WIDTH 8
#define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
@ -959,6 +973,36 @@
#define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
#define LOONGARCH_CSR_DB8ADDR 0x350 /* data breakpoint 8 address */
#define LOONGARCH_CSR_DB8MASK 0x351 /* data breakpoint 8 mask */
#define LOONGARCH_CSR_DB8CTRL 0x352 /* data breakpoint 8 control */
#define LOONGARCH_CSR_DB8ASID 0x353 /* data breakpoint 8 asid */
#define LOONGARCH_CSR_DB9ADDR 0x358 /* data breakpoint 9 address */
#define LOONGARCH_CSR_DB9MASK 0x359 /* data breakpoint 9 mask */
#define LOONGARCH_CSR_DB9CTRL 0x35a /* data breakpoint 9 control */
#define LOONGARCH_CSR_DB9ASID 0x35b /* data breakpoint 9 asid */
#define LOONGARCH_CSR_DB10ADDR 0x360 /* data breakpoint 10 address */
#define LOONGARCH_CSR_DB10MASK 0x361 /* data breakpoint 10 mask */
#define LOONGARCH_CSR_DB10CTRL 0x362 /* data breakpoint 10 control */
#define LOONGARCH_CSR_DB10ASID 0x363 /* data breakpoint 10 asid */
#define LOONGARCH_CSR_DB11ADDR 0x368 /* data breakpoint 11 address */
#define LOONGARCH_CSR_DB11MASK 0x369 /* data breakpoint 11 mask */
#define LOONGARCH_CSR_DB11CTRL 0x36a /* data breakpoint 11 control */
#define LOONGARCH_CSR_DB11ASID 0x36b /* data breakpoint 11 asid */
#define LOONGARCH_CSR_DB12ADDR 0x370 /* data breakpoint 12 address */
#define LOONGARCH_CSR_DB12MASK 0x371 /* data breakpoint 12 mask */
#define LOONGARCH_CSR_DB12CTRL 0x372 /* data breakpoint 12 control */
#define LOONGARCH_CSR_DB12ASID 0x373 /* data breakpoint 12 asid */
#define LOONGARCH_CSR_DB13ADDR 0x378 /* data breakpoint 13 address */
#define LOONGARCH_CSR_DB13MASK 0x379 /* data breakpoint 13 mask */
#define LOONGARCH_CSR_DB13CTRL 0x37a /* data breakpoint 13 control */
#define LOONGARCH_CSR_DB13ASID 0x37b /* data breakpoint 13 asid */
#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
@ -1002,6 +1046,36 @@
#define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
#define LOONGARCH_CSR_IB8ADDR 0x3d0 /* inst breakpoint 8 address */
#define LOONGARCH_CSR_IB8MASK 0x3d1 /* inst breakpoint 8 mask */
#define LOONGARCH_CSR_IB8CTRL 0x3d2 /* inst breakpoint 8 control */
#define LOONGARCH_CSR_IB8ASID 0x3d3 /* inst breakpoint 8 asid */
#define LOONGARCH_CSR_IB9ADDR 0x3d8 /* inst breakpoint 9 address */
#define LOONGARCH_CSR_IB9MASK 0x3d9 /* inst breakpoint 9 mask */
#define LOONGARCH_CSR_IB9CTRL 0x3da /* inst breakpoint 9 control */
#define LOONGARCH_CSR_IB9ASID 0x3db /* inst breakpoint 9 asid */
#define LOONGARCH_CSR_IB10ADDR 0x3e0 /* inst breakpoint 10 address */
#define LOONGARCH_CSR_IB10MASK 0x3e1 /* inst breakpoint 10 mask */
#define LOONGARCH_CSR_IB10CTRL 0x3e2 /* inst breakpoint 10 control */
#define LOONGARCH_CSR_IB10ASID 0x3e3 /* inst breakpoint 10 asid */
#define LOONGARCH_CSR_IB11ADDR 0x3e8 /* inst breakpoint 11 address */
#define LOONGARCH_CSR_IB11MASK 0x3e9 /* inst breakpoint 11 mask */
#define LOONGARCH_CSR_IB11CTRL 0x3ea /* inst breakpoint 11 control */
#define LOONGARCH_CSR_IB11ASID 0x3eb /* inst breakpoint 11 asid */
#define LOONGARCH_CSR_IB12ADDR 0x3f0 /* inst breakpoint 12 address */
#define LOONGARCH_CSR_IB12MASK 0x3f1 /* inst breakpoint 12 mask */
#define LOONGARCH_CSR_IB12CTRL 0x3f2 /* inst breakpoint 12 control */
#define LOONGARCH_CSR_IB12ASID 0x3f3 /* inst breakpoint 12 asid */
#define LOONGARCH_CSR_IB13ADDR 0x3f8 /* inst breakpoint 13 address */
#define LOONGARCH_CSR_IB13MASK 0x3f9 /* inst breakpoint 13 mask */
#define LOONGARCH_CSR_IB13CTRL 0x3fa /* inst breakpoint 13 control */
#define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */
#define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
#define LOONGARCH_CSR_DERA 0x501 /* debug era */
#define LOONGARCH_CSR_DESAVE 0x502 /* debug save */

7
arch/loongarch/include/asm/pgtable-bits.h
View file

@ -96,6 +96,13 @@
#define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_SUC)
#define pgprot_nx pgprot_nx
static inline pgprot_t pgprot_nx(pgprot_t _prot)
{
return __pgprot(pgprot_val(_prot) | _PAGE_NO_EXEC);
}
#define pgprot_noncached pgprot_noncached
static inline pgprot_t pgprot_noncached(pgprot_t _prot)

10
arch/loongarch/include/uapi/asm/ptrace.h
View file

@ -72,6 +72,16 @@ struct user_watch_state {
} dbg_regs[8];
};
struct user_watch_state_v2 {
uint64_t dbg_info;
struct {
uint64_t addr;
uint64_t mask;
uint32_t ctrl;
uint32_t pad;
} dbg_regs[14];
};
#define PTRACE_SYSEMU 0x1f
#define PTRACE_SYSEMU_SINGLESTEP 0x20

2
arch/loongarch/kernel/Makefile
View file

@ -10,7 +10,7 @@ extra-y := vmlinux.lds
obj-y += head.o cpu-probe.o cacheinfo.o env.o setup.o entry.o genex.o \
traps.o irq.o idle.o process.o dma.o mem.o reset.o switch.o \
elf.o syscall.o signal.o time.o topology.o inst.o ptrace.o vdso.o \
alternative.o unwind.o
alternative.o kdebugfs.o unwind.o
obj-$(CONFIG_ACPI) += acpi.o
obj-$(CONFIG_EFI) += efi.o

6
arch/loongarch/kernel/cacheinfo.c
View file

@ -51,6 +51,12 @@ static void cache_cpumap_setup(unsigned int cpu)
continue;
sib_leaf = sib_cpu_ci->info_list + index;
/* SMT cores share all caches */
if (cpus_are_siblings(i, cpu)) {
cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
}
/* Node's cores share shared caches */
if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
cpumask_set_cpu(i, &this_leaf->shared_cpu_map);

1
arch/loongarch/kernel/cpu-probe.c
View file

@ -190,6 +190,7 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
set_cpu_asid_mask(c, asid_mask);
config = read_csr_prcfg1();
c->timerbits = (config & CSR_CONF1_TMRBITS) >> CSR_CONF1_TMRBITS_SHIFT;
c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);
c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK);

16
arch/loongarch/kernel/hw_breakpoint.c
View file

@ -51,7 +51,13 @@ int hw_breakpoint_slots(int type)
READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 7, REG, T, VAL);
READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 10, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 11, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 12, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 13, REG, T, VAL);
#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \
WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \
@ -61,7 +67,13 @@ int hw_breakpoint_slots(int type)
WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);
static u64 read_wb_reg(int reg, int n, int t)
{

168
arch/loongarch/kernel/kdebugfs.c Normal file
View file

@ -0,0 +1,168 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/export.h>
#include <linux/debugfs.h>
#include <linux/kstrtox.h>
#include <asm/loongarch.h>
struct dentry *arch_debugfs_dir;
EXPORT_SYMBOL(arch_debugfs_dir);
static int sfb_state, tso_state;
static void set_sfb_state(void *info)
{
int val = *(int *)info << CSR_STFILL_SHIFT;
csr_xchg32(val, CSR_STFILL, LOONGARCH_CSR_IMPCTL1);
}
static ssize_t sfb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
{
int s, state;
char str[32];
state = (csr_read32(LOONGARCH_CSR_IMPCTL1) & CSR_STFILL) >> CSR_STFILL_SHIFT;
s = snprintf(str, sizeof(str), "Boot State: %x\nCurrent State: %x\n", sfb_state, state);
if (*ppos >= s)
return 0;
s -= *ppos;
s = min_t(u32, s, count);
if (copy_to_user(buf, &str[*ppos], s))
return -EFAULT;
*ppos += s;
return s;
}
static ssize_t sfb_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
{
int state;
if (kstrtoint_from_user(buf, count, 10, &state))
return -EFAULT;
switch (state) {
case 0: case 1:
on_each_cpu(set_sfb_state, &state, 1);
break;
default:
return -EINVAL;
}
return count;
}
static const struct file_operations sfb_fops = {
.read = sfb_read,
.write = sfb_write,
.open = simple_open,
.llseek = default_llseek
};
#define LDSTORDER_NLD_NST 0x0 /* 000 = No Load No Store */
#define LDSTORDER_ALD_NST 0x1 /* 001 = All Load No Store */
#define LDSTORDER_SLD_NST 0x3 /* 011 = Same Load No Store */
#define LDSTORDER_NLD_AST 0x4 /* 100 = No Load All Store */
#define LDSTORDER_ALD_AST 0x5 /* 101 = All Load All Store */
#define LDSTORDER_SLD_AST 0x7 /* 111 = Same Load All Store */
static char *tso_hints[] = {
"No Load No Store",
"All Load No Store",
"Invalid Config",
"Same Load No Store",
"No Load All Store",
"All Load All Store",
"Invalid Config",
"Same Load All Store"
};
static void set_tso_state(void *info)
{
int val = *(int *)info << CSR_LDSTORDER_SHIFT;
csr_xchg32(val, CSR_LDSTORDER_MASK, LOONGARCH_CSR_IMPCTL1);
}
static ssize_t tso_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
{
int s, state;
char str[240];
state = (csr_read32(LOONGARCH_CSR_IMPCTL1) & CSR_LDSTORDER_MASK) >> CSR_LDSTORDER_SHIFT;
s = snprintf(str, sizeof(str), "Boot State: %d (%s)\n"
"Current State: %d (%s)\n\n"
"Available States:\n"
"0 (%s)\t" "1 (%s)\t" "3 (%s)\n"
"4 (%s)\t" "5 (%s)\t" "7 (%s)\n",
tso_state, tso_hints[tso_state], state, tso_hints[state],
tso_hints[0], tso_hints[1], tso_hints[3], tso_hints[4], tso_hints[5], tso_hints[7]);
if (*ppos >= s)
return 0;
s -= *ppos;
s = min_t(u32, s, count);
if (copy_to_user(buf, &str[*ppos], s))
return -EFAULT;
*ppos += s;
return s;
}
static ssize_t tso_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
{
int state;
if (kstrtoint_from_user(buf, count, 10, &state))
return -EFAULT;
switch (state) {
case 0: case 1: case 3:
case 4: case 5: case 7:
on_each_cpu(set_tso_state, &state, 1);
break;
default:
return -EINVAL;
}
return count;
}
static const struct file_operations tso_fops = {
.read = tso_read,
.write = tso_write,
.open = simple_open,
.llseek = default_llseek
};
static int __init arch_kdebugfs_init(void)
{
unsigned int config = read_cpucfg(LOONGARCH_CPUCFG3);
arch_debugfs_dir = debugfs_create_dir("loongarch", NULL);
if (config & CPUCFG3_SFB) {
debugfs_create_file("sfb_state", S_IRUGO | S_IWUSR,
arch_debugfs_dir, &sfb_state, &sfb_fops);
sfb_state = (csr_read32(LOONGARCH_CSR_IMPCTL1) & CSR_STFILL) >> CSR_STFILL_SHIFT;
}
if (config & (CPUCFG3_ALDORDER_CAP | CPUCFG3_ASTORDER_CAP)) {
debugfs_create_file("tso_state", S_IRUGO | S_IWUSR,
arch_debugfs_dir, &tso_state, &tso_fops);
tso_state = (csr_read32(LOONGARCH_CSR_IMPCTL1) & CSR_LDSTORDER_MASK) >> CSR_LDSTORDER_SHIFT;
}
return 0;
}
postcore_initcall(arch_kdebugfs_init);

6
arch/loongarch/kernel/ptrace.c
View file

@ -720,7 +720,7 @@ static int hw_break_set(struct task_struct *target,
unsigned int note_type = regset->core_note_type;
/* Resource info */
offset = offsetof(struct user_watch_state, dbg_regs);
offset = offsetof(struct user_watch_state_v2, dbg_regs);
user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset);
/* (address, mask, ctrl) registers */
@ -920,7 +920,7 @@ static const struct user_regset loongarch64_regsets[] = {
#ifdef CONFIG_HAVE_HW_BREAKPOINT
[REGSET_HW_BREAK] = {
.core_note_type = NT_LOONGARCH_HW_BREAK,
.n = sizeof(struct user_watch_state) / sizeof(u32),
.n = sizeof(struct user_watch_state_v2) / sizeof(u32),
.size = sizeof(u32),
.align = sizeof(u32),
.regset_get = hw_break_get,
@ -928,7 +928,7 @@ static const struct user_regset loongarch64_regsets[] = {
},
[REGSET_HW_WATCH] = {
.core_note_type = NT_LOONGARCH_HW_WATCH,
.n = sizeof(struct user_watch_state) / sizeof(u32),
.n = sizeof(struct user_watch_state_v2) / sizeof(u32),
.size = sizeof(u32),
.align = sizeof(u32),
.regset_get = hw_break_get,

2
arch/loongarch/kernel/switch.S
View file

@ -12,7 +12,7 @@
/*
* task_struct *__switch_to(task_struct *prev, task_struct *next,
* struct thread_info *next_ti)
* struct thread_info *next_ti, void *sched_ra, void *sched_cfa)
*/
.align 5
SYM_FUNC_START(__switch_to)

2
arch/loongarch/kernel/time.c
View file

@ -132,7 +132,7 @@ int constant_clockevent_init(void)
#else
unsigned long min_delta = 1000;
#endif
unsigned long max_delta = (1UL << 48) - 1;
unsigned long max_delta = GENMASK_ULL(boot_cpu_data.timerbits, 0);
struct clock_event_device *cd;
static int irq = 0, timer_irq_installed = 0;

13
arch/loongarch/kernel/traps.c
View file

@ -597,17 +597,24 @@ int is_valid_bugaddr(unsigned long addr)
static void bug_handler(struct pt_regs *regs)
{
if (user_mode(regs)) {
force_sig(SIGTRAP);
return;
}
switch (report_bug(regs->csr_era, regs)) {
case BUG_TRAP_TYPE_BUG:
case BUG_TRAP_TYPE_NONE:
die_if_kernel("Oops - BUG", regs);
force_sig(SIGTRAP);
die("Oops - BUG", regs);
break;
case BUG_TRAP_TYPE_WARN:
/* Skip the BUG instruction and continue */
regs->csr_era += LOONGARCH_INSN_SIZE;
break;
default:
if (!fixup_exception(regs))
die("Oops - BUG", regs);
}
}

8
arch/loongarch/kernel/unaligned.c
View file

@ -482,14 +482,10 @@ sigbus:
#ifdef CONFIG_DEBUG_FS
static int __init debugfs_unaligned(void)
{
struct dentry *d;
d = debugfs_create_dir("loongarch", NULL);
debugfs_create_u32("unaligned_instructions_user",
S_IRUGO, d, &unaligned_instructions_user);
S_IRUGO, arch_debugfs_dir, &unaligned_instructions_user);
debugfs_create_u32("unaligned_instructions_kernel",
S_IRUGO, d, &unaligned_instructions_kernel);
S_IRUGO, arch_debugfs_dir, &unaligned_instructions_kernel);
return 0;
}

2
arch/loongarch/power/platform.c
View file

@ -17,7 +17,7 @@ void enable_gpe_wakeup(void)
if (acpi_gbl_reduced_hardware)
return;
acpi_enable_all_wakeup_gpes();
acpi_hw_enable_all_wakeup_gpes();
}
void enable_pci_wakeup(void)

10
arch/loongarch/power/suspend_asm.S
View file

@ -30,9 +30,6 @@
st.d $r29, sp, PT_R29
st.d $r30, sp, PT_R30
st.d $r31, sp, PT_R31
la.pcrel t0, acpi_saved_sp
st.d sp, t0, 0
.endm
.macro SETUP_WAKEUP
@ -51,6 +48,7 @@
ld.d $r29, sp, PT_R29
ld.d $r30, sp, PT_R30
ld.d $r31, sp, PT_R31
addi.d sp, sp, PT_SIZE
.endm
.text
@ -59,6 +57,10 @@
/* Sleep/wakeup code for Loongson-3 */
SYM_FUNC_START(loongarch_suspend_enter)
SETUP_SLEEP
la.pcrel t0, acpi_saved_sp
st.d sp, t0, 0
bl __flush_cache_all
/* Pass RA and SP to BIOS */
@ -82,7 +84,7 @@ SYM_INNER_LABEL(loongarch_wakeup_start, SYM_L_GLOBAL)
la.pcrel t0, acpi_saved_sp
ld.d sp, t0, 0
SETUP_WAKEUP
addi.d sp, sp, PT_SIZE
jr ra
SYM_FUNC_END(loongarch_suspend_enter)

2
drivers/acpi/acpica/achware.h
View file

@ -103,8 +103,6 @@ acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
acpi_status acpi_hw_enable_all_runtime_gpes(void);
acpi_status acpi_hw_enable_all_wakeup_gpes(void);
u8 acpi_hw_check_all_gpes(acpi_handle gpe_skip_device, u32 gpe_skip_number);
acpi_status

1
include/acpi/acpixf.h
View file

@ -763,6 +763,7 @@ ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
*event_status))
ACPI_HW_DEPENDENT_RETURN_UINT32(u32 acpi_dispatch_gpe(acpi_handle gpe_device, u32 gpe_number))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_hw_disable_all_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_hw_enable_all_wakeup_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_disable_all_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_runtime_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_wakeup_gpes(void))