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perf vendor events intel: Update WSM-EP-SP events to v3

Browse source 
Events are generated for Westmere EP-SP v3 with events from:

  https://download.01.org/perfmon/WSM-EP-SP/

Using the scripts at:

  https://github.com/intel/event-converter-for-linux-perf/

This change updates descriptions.

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220428075730.797727-6-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2022-04-28 00:57:29 -07:00 • committed by Arnaldo Carvalho de Melo
parent e14fd2ee6d
commit a0cb448978
2 changed files with 10 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
View file

@ -1769,7 +1769,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
@ -1780,7 +1780,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
@ -1791,7 +1791,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
@ -1802,7 +1802,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core",
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
@ -1857,7 +1857,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache",
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
@ -1868,7 +1868,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",

4
tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
View file

@ -286,7 +286,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
@ -297,7 +297,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",