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thermal/drivers/qcom/tsens-v0_1: Add support for MDM9607

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MDM9607 TSENS IP is very similar to the one of MSM8916, with
minor adjustments to various tuning values.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20210319220802.198215-2-konrad.dybcio@somainline.org
This commit is contained in:
Konrad Dybcio 2021-03-19 23:08:02 +01:00 • committed by Daniel Lezcano
parent c061226529
commit a2149ab815
3 changed files with 101 additions and 2 deletions
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98
drivers/thermal/qcom/tsens-v0_1.c
View file

@ -190,6 +190,39 @@
#define BIT_APPEND 0x3 #define BIT_APPEND 0x3
/* eeprom layout data for mdm9607 */
#define MDM9607_BASE0_MASK 0x000000ff
#define MDM9607_BASE1_MASK 0x000ff000
#define MDM9607_BASE0_SHIFT 0
#define MDM9607_BASE1_SHIFT 12
#define MDM9607_S0_P1_MASK 0x00003f00
#define MDM9607_S1_P1_MASK 0x03f00000
#define MDM9607_S2_P1_MASK 0x0000003f
#define MDM9607_S3_P1_MASK 0x0003f000
#define MDM9607_S4_P1_MASK 0x0000003f
#define MDM9607_S0_P2_MASK 0x000fc000
#define MDM9607_S1_P2_MASK 0xfc000000
#define MDM9607_S2_P2_MASK 0x00000fc0
#define MDM9607_S3_P2_MASK 0x00fc0000
#define MDM9607_S4_P2_MASK 0x00000fc0
#define MDM9607_S0_P1_SHIFT 8
#define MDM9607_S1_P1_SHIFT 20
#define MDM9607_S2_P1_SHIFT 0
#define MDM9607_S3_P1_SHIFT 12
#define MDM9607_S4_P1_SHIFT 0
#define MDM9607_S0_P2_SHIFT 14
#define MDM9607_S1_P2_SHIFT 26
#define MDM9607_S2_P2_SHIFT 6
#define MDM9607_S3_P2_SHIFT 18
#define MDM9607_S4_P2_SHIFT 6
#define MDM9607_CAL_SEL_MASK 0x00700000
#define MDM9607_CAL_SEL_SHIFT 20
static int calibrate_8916(struct tsens_priv *priv) static int calibrate_8916(struct tsens_priv *priv)
{ {
int base0 = 0, base1 = 0, i; int base0 = 0, base1 = 0, i;
@ -452,7 +485,56 @@ static int calibrate_8974(struct tsens_priv *priv)
return 0; return 0;
} }
/* v0.1: 8916, 8939, 8974 */ static int calibrate_9607(struct tsens_priv *priv)
{
int base, i;
u32 p1[5], p2[5];
int mode = 0;
u32 *qfprom_cdata;
qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
if (IS_ERR(qfprom_cdata))
return PTR_ERR(qfprom_cdata);
mode = (qfprom_cdata[2] & MDM9607_CAL_SEL_MASK) >> MDM9607_CAL_SEL_SHIFT;
dev_dbg(priv->dev, "calibration mode is %d\n", mode);
switch (mode) {
case TWO_PT_CALIB:
base = (qfprom_cdata[2] & MDM9607_BASE1_MASK) >> MDM9607_BASE1_SHIFT;
p2[0] = (qfprom_cdata[0] & MDM9607_S0_P2_MASK) >> MDM9607_S0_P2_SHIFT;
p2[1] = (qfprom_cdata[0] & MDM9607_S1_P2_MASK) >> MDM9607_S1_P2_SHIFT;
p2[2] = (qfprom_cdata[1] & MDM9607_S2_P2_MASK) >> MDM9607_S2_P2_SHIFT;
p2[3] = (qfprom_cdata[1] & MDM9607_S3_P2_MASK) >> MDM9607_S3_P2_SHIFT;
p2[4] = (qfprom_cdata[2] & MDM9607_S4_P2_MASK) >> MDM9607_S4_P2_SHIFT;
for (i = 0; i < priv->num_sensors; i++)
p2[i] = ((base + p2[i]) << 2);
fallthrough;
case ONE_PT_CALIB2:
base = (qfprom_cdata[0] & MDM9607_BASE0_MASK);
p1[0] = (qfprom_cdata[0] & MDM9607_S0_P1_MASK) >> MDM9607_S0_P1_SHIFT;
p1[1] = (qfprom_cdata[0] & MDM9607_S1_P1_MASK) >> MDM9607_S1_P1_SHIFT;
p1[2] = (qfprom_cdata[1] & MDM9607_S2_P1_MASK) >> MDM9607_S2_P1_SHIFT;
p1[3] = (qfprom_cdata[1] & MDM9607_S3_P1_MASK) >> MDM9607_S3_P1_SHIFT;
p1[4] = (qfprom_cdata[2] & MDM9607_S4_P1_MASK) >> MDM9607_S4_P1_SHIFT;
for (i = 0; i < priv->num_sensors; i++)
p1[i] = ((base + p1[i]) << 2);
break;
default:
for (i = 0; i < priv->num_sensors; i++) {
p1[i] = 500;
p2[i] = 780;
}
break;
}
compute_intercept_slope(priv, p1, p2, mode);
kfree(qfprom_cdata);
return 0;
}
/* v0.1: 8916, 8939, 8974, 9607 */
static struct tsens_features tsens_v0_1_feat = { static struct tsens_features tsens_v0_1_feat = {
.ver_major = VER_0_1, .ver_major = VER_0_1,
@ -540,3 +622,17 @@ struct tsens_plat_data data_8974 = {
.feat = &tsens_v0_1_feat, .feat = &tsens_v0_1_feat,
.fields = tsens_v0_1_regfields, .fields = tsens_v0_1_regfields,
}; };
static const struct tsens_ops ops_9607 = {
.init = init_common,
.calibrate = calibrate_9607,
.get_temp = get_temp_common,
};
struct tsens_plat_data data_9607 = {
.num_sensors = 5,
.ops = &ops_9607,
.hw_ids = (unsigned int []){ 0, 1, 2, 3, 4 },
.feat = &tsens_v0_1_feat,
.fields = tsens_v0_1_regfields,
};

3
drivers/thermal/qcom/tsens.c
View file

@ -897,6 +897,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
static const struct of_device_id tsens_table[] = { static const struct of_device_id tsens_table[] = {
{ {
.compatible = "qcom,mdm9607-tsens",
.data = &data_9607,
}, {
.compatible = "qcom,msm8916-tsens", .compatible = "qcom,msm8916-tsens",
.data = &data_8916, .data = &data_8916,
}, { }, {

2
drivers/thermal/qcom/tsens.h
View file

@ -585,7 +585,7 @@ int get_temp_common(const struct tsens_sensor *s, int *temp);
extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8960;
/* TSENS v0.1 targets */ /* TSENS v0.1 targets */
extern struct tsens_plat_data data_8916, data_8939, data_8974; extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607;
/* TSENS v1 targets */ /* TSENS v1 targets */
extern struct tsens_plat_data data_tsens_v1, data_8976; extern struct tsens_plat_data data_tsens_v1, data_8976;