usb: dwc2: gadget: Disable enabled HW endpoint in dwc2_hsotg_ep_disable
Check if endpoint is enabled during dwc2_hsotg_ep_disable() function processing and call dwc2_hsotg_ep_stop_xfr() to disable it and flush associated FIFO. Move dwc2_hsotg_ep_stop_xfr() and dwc2_hsotg_wait_bit_set() functions upper before dwc2_hsotg_ep_enable and dwc2_hsotg_ep_disable function definitions. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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1 changed files with 93 additions and 89 deletions
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@ -3585,6 +3585,95 @@ irq_retry:
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
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u32 bit, u32 timeout)
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{
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u32 i;
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for (i = 0; i < timeout; i++) {
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if (dwc2_readl(hs_otg->regs + reg) & bit)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
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struct dwc2_hsotg_ep *hs_ep)
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{
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u32 epctrl_reg;
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u32 epint_reg;
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epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
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DOEPCTL(hs_ep->index);
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epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
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DOEPINT(hs_ep->index);
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dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
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hs_ep->name);
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if (hs_ep->dir_in) {
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if (hsotg->dedicated_fifos || hs_ep->periodic) {
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__orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
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/* Wait for Nak effect */
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if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
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DXEPINT_INEPNAKEFF, 100))
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dev_warn(hsotg->dev,
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"%s: timeout DIEPINT.NAKEFF\n",
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__func__);
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} else {
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__orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK);
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/* Wait for Nak effect */
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if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
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GINTSTS_GINNAKEFF, 100))
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dev_warn(hsotg->dev,
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"%s: timeout GINTSTS.GINNAKEFF\n",
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__func__);
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}
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} else {
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if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
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__orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
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/* Wait for global nak to take effect */
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if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
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GINTSTS_GOUTNAKEFF, 100))
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dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
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__func__);
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}
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/* Disable ep */
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__orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
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/* Wait for ep to be disabled */
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if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
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dev_warn(hsotg->dev,
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"%s: timeout DOEPCTL.EPDisable\n", __func__);
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/* Clear EPDISBLD interrupt */
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__orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
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if (hs_ep->dir_in) {
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unsigned short fifo_index;
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if (hsotg->dedicated_fifos || hs_ep->periodic)
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fifo_index = hs_ep->fifo_index;
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else
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fifo_index = 0;
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/* Flush TX FIFO */
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dwc2_flush_tx_fifo(hsotg, fifo_index);
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/* Clear Global In NP NAK in Shared FIFO for non periodic ep */
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if (!hsotg->dedicated_fifos && !hs_ep->periodic)
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__orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
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} else {
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/* Remove global NAKs */
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__orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
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}
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}
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/**
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/**
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* dwc2_hsotg_ep_enable - enable the given endpoint
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* dwc2_hsotg_ep_enable - enable the given endpoint
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* @ep: The USB endpint to configure
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* @ep: The USB endpint to configure
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@ -3803,6 +3892,10 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
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spin_lock_irqsave(&hsotg->lock, flags);
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spin_lock_irqsave(&hsotg->lock, flags);
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ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
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ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
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if (ctrl & DXEPCTL_EPENA)
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dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
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ctrl &= ~DXEPCTL_EPENA;
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ctrl &= ~DXEPCTL_EPENA;
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ctrl &= ~DXEPCTL_USBACTEP;
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ctrl &= ~DXEPCTL_USBACTEP;
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ctrl |= DXEPCTL_SNAK;
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ctrl |= DXEPCTL_SNAK;
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@ -3841,95 +3934,6 @@ static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
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return false;
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return false;
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}
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}
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static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
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u32 bit, u32 timeout)
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{
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u32 i;
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for (i = 0; i < timeout; i++) {
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if (dwc2_readl(hs_otg->regs + reg) & bit)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
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struct dwc2_hsotg_ep *hs_ep)
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{
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u32 epctrl_reg;
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u32 epint_reg;
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epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
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DOEPCTL(hs_ep->index);
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epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
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DOEPINT(hs_ep->index);
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dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
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hs_ep->name);
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if (hs_ep->dir_in) {
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if (hsotg->dedicated_fifos || hs_ep->periodic) {
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__orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
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/* Wait for Nak effect */
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if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
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DXEPINT_INEPNAKEFF, 100))
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dev_warn(hsotg->dev,
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"%s: timeout DIEPINT.NAKEFF\n",
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__func__);
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} else {
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__orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK);
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/* Wait for Nak effect */
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if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
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GINTSTS_GINNAKEFF, 100))
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dev_warn(hsotg->dev,
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"%s: timeout GINTSTS.GINNAKEFF\n",
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__func__);
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}
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} else {
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if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
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__orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
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/* Wait for global nak to take effect */
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if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
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GINTSTS_GOUTNAKEFF, 100))
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dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
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__func__);
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}
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/* Disable ep */
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__orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
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/* Wait for ep to be disabled */
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if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
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dev_warn(hsotg->dev,
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"%s: timeout DOEPCTL.EPDisable\n", __func__);
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/* Clear EPDISBLD interrupt */
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__orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
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if (hs_ep->dir_in) {
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unsigned short fifo_index;
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if (hsotg->dedicated_fifos || hs_ep->periodic)
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fifo_index = hs_ep->fifo_index;
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else
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fifo_index = 0;
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/* Flush TX FIFO */
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dwc2_flush_tx_fifo(hsotg, fifo_index);
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/* Clear Global In NP NAK in Shared FIFO for non periodic ep */
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if (!hsotg->dedicated_fifos && !hs_ep->periodic)
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__orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
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} else {
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/* Remove global NAKs */
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__orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
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}
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}
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/**
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/**
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* dwc2_hsotg_ep_dequeue - dequeue given endpoint
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* dwc2_hsotg_ep_dequeue - dequeue given endpoint
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* @ep: The endpoint to dequeue.
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* @ep: The endpoint to dequeue.
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