drm/amdkfd: Update SDMA queue management for GFX9.4.3
This patch updates SDMA queue management for multi XCC in GFX9.4.3. - Allocate/deallocate SDMA queues from the correct SDMA engines based on the partition mode. - Updates the kgd2kfd interface to fetch the correct SDMA register addresses. - It also fixes dumping correct SDMA queue info in debugfs. v2: squash in fix "drm/amdkfd: Fix XGMI SDMA user-mode queue allocation" Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi
Alex Deucher
parent
f38f147ab3
commit
a805889a15
5 changed files with 227 additions and 41 deletions
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@ -31,6 +31,192 @@
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#include "oss/osssys_4_0_sh_mask.h"
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#include "v9_structs.h"
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#include "soc15.h"
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#include "sdma/sdma_4_4_2_offset.h"
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#include "sdma/sdma_4_4_2_sh_mask.h"
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static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
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{
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return (struct v9_sdma_mqd *)mqd;
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}
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static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
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unsigned int engine_id,
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unsigned int queue_id)
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{
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uint32_t sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, engine_id,
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regSDMA_RLC0_RB_CNTL) -
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regSDMA_RLC0_RB_CNTL;
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uint32_t retval = sdma_engine_reg_base +
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queue_id * (regSDMA_RLC1_RB_CNTL - regSDMA_RLC0_RB_CNTL);
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pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
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queue_id, retval);
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return retval;
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}
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int kgd_gfx_v9_4_3_hqd_sdma_load(struct amdgpu_device *adev, void *mqd,
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uint32_t __user *wptr, struct mm_struct *mm)
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{
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struct v9_sdma_mqd *m;
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uint32_t sdma_rlc_reg_offset;
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unsigned long end_jiffies;
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uint32_t data;
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uint64_t data64;
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uint64_t __user *wptr64 = (uint64_t __user *)wptr;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
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m->sdma_queue_id);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL,
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m->sdmax_rlcx_rb_cntl & (~SDMA_RLC0_RB_CNTL__RB_ENABLE_MASK));
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end_jiffies = msecs_to_jiffies(2000) + jiffies;
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while (true) {
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data = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);
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if (data & SDMA_RLC0_CONTEXT_STATUS__IDLE_MASK)
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break;
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if (time_after(jiffies, end_jiffies)) {
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pr_err("SDMA RLC not idle in %s\n", __func__);
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return -ETIME;
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}
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usleep_range(500, 1000);
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}
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL_OFFSET,
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m->sdmax_rlcx_doorbell_offset);
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data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA_RLC0_DOORBELL,
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ENABLE, 1);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL, data);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR,
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m->sdmax_rlcx_rb_rptr);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI,
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m->sdmax_rlcx_rb_rptr_hi);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_MINOR_PTR_UPDATE, 1);
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if (read_user_wptr(mm, wptr64, data64)) {
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR,
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lower_32_bits(data64));
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR_HI,
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upper_32_bits(data64));
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} else {
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR,
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m->sdmax_rlcx_rb_rptr);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR_HI,
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m->sdmax_rlcx_rb_rptr_hi);
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}
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_MINOR_PTR_UPDATE, 0);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_BASE_HI,
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m->sdmax_rlcx_rb_base_hi);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_ADDR_LO,
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m->sdmax_rlcx_rb_rptr_addr_lo);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_ADDR_HI,
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m->sdmax_rlcx_rb_rptr_addr_hi);
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data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA_RLC0_RB_CNTL,
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RB_ENABLE, 1);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, data);
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return 0;
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}
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int kgd_gfx_v9_4_3_hqd_sdma_dump(struct amdgpu_device *adev,
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uint32_t engine_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs)
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{
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uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
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engine_id, queue_id);
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uint32_t i = 0, reg;
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#undef HQD_N_REGS
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#define HQD_N_REGS (19+6+7+12)
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#define DUMP_REG(addr) do { \
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if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
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break; \
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(*dump)[i][0] = (addr) << 2; \
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(*dump)[i++][1] = RREG32(addr); \
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} while (0)
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*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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return -ENOMEM;
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for (reg = regSDMA_RLC0_RB_CNTL; reg <= regSDMA_RLC0_DOORBELL; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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for (reg = regSDMA_RLC0_STATUS; reg <= regSDMA_RLC0_CSA_ADDR_HI; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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for (reg = regSDMA_RLC0_IB_SUB_REMAIN;
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reg <= regSDMA_RLC0_MINOR_PTR_UPDATE; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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for (reg = regSDMA_RLC0_MIDCMD_DATA0;
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reg <= regSDMA_RLC0_MIDCMD_CNTL; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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WARN_ON_ONCE(i != HQD_N_REGS);
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*n_regs = i;
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return 0;
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}
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bool kgd_gfx_v9_4_3_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
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{
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struct v9_sdma_mqd *m;
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uint32_t sdma_rlc_reg_offset;
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uint32_t sdma_rlc_rb_cntl;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
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m->sdma_queue_id);
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sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);
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if (sdma_rlc_rb_cntl & SDMA_RLC0_RB_CNTL__RB_ENABLE_MASK)
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return true;
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return false;
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}
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int kgd_gfx_v9_4_3_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd,
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unsigned int utimeout)
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{
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struct v9_sdma_mqd *m;
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uint32_t sdma_rlc_reg_offset;
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uint32_t temp;
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unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
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m->sdma_queue_id);
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temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);
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temp = temp & ~SDMA_RLC0_RB_CNTL__RB_ENABLE_MASK;
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, temp);
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while (true) {
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temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);
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if (temp & SDMA_RLC0_CONTEXT_STATUS__IDLE_MASK)
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break;
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if (time_after(jiffies, end_jiffies)) {
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pr_err("SDMA RLC not idle in %s\n", __func__);
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return -ETIME;
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}
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usleep_range(500, 1000);
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}
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL, 0);
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WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL,
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RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL) |
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SDMA_RLC0_RB_CNTL__RB_ENABLE_MASK);
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m->sdmax_rlcx_rb_rptr =
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RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR);
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m->sdmax_rlcx_rb_rptr_hi =
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RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI);
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return 0;
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}
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static int kgd_gfx_v9_4_3_set_pasid_vmid_mapping(struct amdgpu_device *adev,
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u32 pasid, unsigned int vmid, uint32_t inst)
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@ -166,13 +352,13 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = {
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.init_interrupts = kgd_gfx_v9_init_interrupts,
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.hqd_load = kgd_gfx_v9_4_3_hqd_load,
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.hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load,
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.hqd_sdma_load = kgd_arcturus_hqd_sdma_load,
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.hqd_sdma_load = kgd_gfx_v9_4_3_hqd_sdma_load,
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.hqd_dump = kgd_gfx_v9_hqd_dump,
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.hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump,
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.hqd_sdma_dump = kgd_gfx_v9_4_3_hqd_sdma_dump,
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.hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
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.hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,
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.hqd_sdma_is_occupied = kgd_gfx_v9_4_3_hqd_sdma_is_occupied,
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.hqd_destroy = kgd_gfx_v9_hqd_destroy,
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.hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,
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.hqd_sdma_destroy = kgd_gfx_v9_4_3_hqd_sdma_destroy,
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.wave_control_execute = kgd_gfx_v9_wave_control_execute,
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.get_atc_vmid_pasid_mapping_info =
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kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
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@ -741,6 +741,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
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if (!node)
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goto node_alloc_error;
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node->node_id = i;
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node->adev = kfd->adev;
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node->kfd = kfd;
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node->kfd2kgd = kfd->kfd2kgd;
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@ -1323,15 +1324,16 @@ unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
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{
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/* If XGMI is not supported, all SDMA engines are PCIe */
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if (!node->adev->gmc.xgmi.supported)
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return node->adev->sdma.num_instances;
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return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
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return min(node->adev->sdma.num_instances, 2);
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return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
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}
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unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
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{
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/* After reserved for PCIe, the rest of engines are XGMI */
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return node->adev->sdma.num_instances - kfd_get_num_sdma_engines(node);
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return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
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kfd_get_num_sdma_engines(node);
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}
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#if defined(CONFIG_DEBUG_FS)
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@ -124,6 +124,15 @@ static inline uint64_t get_reserved_sdma_queues_bitmap(struct device_queue_manag
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return dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap;
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}
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static void init_sdma_bitmaps(struct device_queue_manager *dqm)
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{
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bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
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bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm));
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bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
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bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
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}
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void program_sh_mem_settings(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd)
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{
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@ -1268,24 +1277,6 @@ static void init_interrupts(struct device_queue_manager *dqm)
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}
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}
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static void init_sdma_bitmaps(struct device_queue_manager *dqm)
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{
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unsigned int num_sdma_queues =
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min_t(unsigned int, sizeof(dqm->sdma_bitmap)*8,
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get_num_sdma_queues(dqm));
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unsigned int num_xgmi_sdma_queues =
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min_t(unsigned int, sizeof(dqm->xgmi_sdma_bitmap)*8,
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get_num_xgmi_sdma_queues(dqm));
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if (num_sdma_queues)
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dqm->sdma_bitmap = GENMASK_ULL(num_sdma_queues-1, 0);
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if (num_xgmi_sdma_queues)
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dqm->xgmi_sdma_bitmap = GENMASK_ULL(num_xgmi_sdma_queues-1, 0);
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dqm->sdma_bitmap &= ~get_reserved_sdma_queues_bitmap(dqm);
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pr_info("sdma_bitmap: %llx\n", dqm->sdma_bitmap);
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}
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static int initialize_nocpsch(struct device_queue_manager *dqm)
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{
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int pipe, queue;
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@ -1375,46 +1366,49 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm,
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int bit;
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if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
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if (dqm->sdma_bitmap == 0) {
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if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
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pr_err("No more SDMA queue to allocate\n");
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return -ENOMEM;
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}
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if (restore_sdma_id) {
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/* Re-use existing sdma_id */
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if (!(dqm->sdma_bitmap & (1ULL << *restore_sdma_id))) {
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if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) {
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pr_err("SDMA queue already in use\n");
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return -EBUSY;
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}
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dqm->sdma_bitmap &= ~(1ULL << *restore_sdma_id);
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clear_bit(*restore_sdma_id, dqm->sdma_bitmap);
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q->sdma_id = *restore_sdma_id;
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} else {
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/* Find first available sdma_id */
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bit = __ffs64(dqm->sdma_bitmap);
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dqm->sdma_bitmap &= ~(1ULL << bit);
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bit = find_first_bit(dqm->sdma_bitmap,
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get_num_sdma_queues(dqm));
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clear_bit(bit, dqm->sdma_bitmap);
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q->sdma_id = bit;
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}
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q->properties.sdma_engine_id = q->sdma_id %
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kfd_get_num_sdma_engines(dqm->dev);
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q->properties.sdma_engine_id =
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dqm->dev->node_id * get_num_all_sdma_engines(dqm) +
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q->sdma_id % kfd_get_num_sdma_engines(dqm->dev);
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q->properties.sdma_queue_id = q->sdma_id /
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kfd_get_num_sdma_engines(dqm->dev);
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} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
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if (dqm->xgmi_sdma_bitmap == 0) {
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if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
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pr_err("No more XGMI SDMA queue to allocate\n");
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return -ENOMEM;
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}
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if (restore_sdma_id) {
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/* Re-use existing sdma_id */
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if (!(dqm->xgmi_sdma_bitmap & (1ULL << *restore_sdma_id))) {
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if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) {
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pr_err("SDMA queue already in use\n");
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return -EBUSY;
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}
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dqm->xgmi_sdma_bitmap &= ~(1ULL << *restore_sdma_id);
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clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap);
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q->sdma_id = *restore_sdma_id;
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} else {
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bit = __ffs64(dqm->xgmi_sdma_bitmap);
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dqm->xgmi_sdma_bitmap &= ~(1ULL << bit);
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bit = find_first_bit(dqm->xgmi_sdma_bitmap,
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get_num_xgmi_sdma_queues(dqm));
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clear_bit(bit, dqm->xgmi_sdma_bitmap);
|
||||
q->sdma_id = bit;
|
||||
}
|
||||
/* sdma_engine_id is sdma id including
|
||||
|
|
@ -1424,6 +1418,7 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm,
|
|||
* PCIe-optimized ones
|
||||
*/
|
||||
q->properties.sdma_engine_id =
|
||||
dqm->dev->node_id * get_num_all_sdma_engines(dqm) +
|
||||
kfd_get_num_sdma_engines(dqm->dev) +
|
||||
q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev);
|
||||
q->properties.sdma_queue_id = q->sdma_id /
|
||||
|
|
@ -1442,11 +1437,11 @@ static void deallocate_sdma_queue(struct device_queue_manager *dqm,
|
|||
if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
|
||||
if (q->sdma_id >= get_num_sdma_queues(dqm))
|
||||
return;
|
||||
dqm->sdma_bitmap |= (1ULL << q->sdma_id);
|
||||
set_bit(q->sdma_id, dqm->sdma_bitmap);
|
||||
} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
|
||||
if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
|
||||
return;
|
||||
dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id);
|
||||
set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -239,8 +239,8 @@ struct device_queue_manager {
|
|||
unsigned int total_queue_count;
|
||||
unsigned int next_pipe_to_allocate;
|
||||
unsigned int *allocated_queues;
|
||||
uint64_t sdma_bitmap;
|
||||
uint64_t xgmi_sdma_bitmap;
|
||||
DECLARE_BITMAP(sdma_bitmap, KFD_MAX_SDMA_QUEUES);
|
||||
DECLARE_BITMAP(xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
|
||||
/* the pasid mapping for each kfd vmid */
|
||||
uint16_t vmid_pasid[VMID_NUM];
|
||||
uint64_t pipelines_addr;
|
||||
|
|
|
|||
|
|
@ -113,6 +113,8 @@
|
|||
|
||||
#define KFD_UNMAP_LATENCY_MS (4000)
|
||||
|
||||
#define KFD_MAX_SDMA_QUEUES 128
|
||||
|
||||
/*
|
||||
* 512 = 0x200
|
||||
* The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the
|
||||
|
|
@ -260,6 +262,7 @@ struct kfd_vmid_info {
|
|||
struct kfd_dev;
|
||||
|
||||
struct kfd_node {
|
||||
unsigned int node_id;
|
||||
struct amdgpu_device *adev; /* Duplicated here along with keeping
|
||||
* a copy in kfd_dev to save a hop
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue