niansa-misc/linux
1
0
Fork 0
mirror of synced 2025-03-06 20:59:54 +01:00
Code Issues Projects Releases Packages Wiki Activity

mei: trace pci configuration space io

Browse source 
Use tracing events also for reading and writing pci configuration space
<debugfs>/tracing/events/mei/mei_pci_reg_{read,write}

Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Tomas Winkler 2016-02-07 22:46:51 +02:00 • committed by Greg Kroah-Hartman
parent 3a20a5c339
commit a96c548291
4 changed files with 56 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
drivers/misc/mei/hw-me.c
View file

@ -189,8 +189,11 @@ static int mei_me_fw_status(struct mei_device *dev,
fw_status->count = fw_src->count; fw_status->count = fw_src->count;
for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
ret = pci_read_config_dword(pdev, ret = pci_read_config_dword(pdev, fw_src->status[i],
fw_src->status[i], &fw_status->status[i]); &fw_status->status[i]);
trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
fw_src->status[i],
fw_status->status[i]);
if (ret) if (ret)
return ret; return ret;
} }
@ -215,6 +218,7 @@ static void mei_me_hw_config(struct mei_device *dev)
reg = 0; reg = 0;
pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg); pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
hw->d0i3_supported = hw->d0i3_supported =
((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK); ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
@ -1248,6 +1252,7 @@ static bool mei_me_fw_type_nm(struct pci_dev *pdev)
u32 reg; u32 reg;
pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg); pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
return (reg & 0x600) == 0x200; return (reg & 0x600) == 0x200;
} }
@ -1260,6 +1265,7 @@ static bool mei_me_fw_type_sps(struct pci_dev *pdev)
u32 reg; u32 reg;
/* Read ME FW Status check for SPS Firmware */ /* Read ME FW Status check for SPS Firmware */
pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg); pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
/* if bits [19:16] = 15, running SPS Firmware */ /* if bits [19:16] = 15, running SPS Firmware */
return (reg & 0xf0000) == 0xf0000; return (reg & 0xf0000) == 0xf0000;
} }

10
drivers/misc/mei/hw-txe.c
View file

@ -28,6 +28,9 @@
#include "client.h" #include "client.h"
#include "hbm.h" #include "hbm.h"
#include "mei-trace.h"
/** /**
* mei_txe_reg_read - Reads 32bit data from the txe device * mei_txe_reg_read - Reads 32bit data from the txe device
* *
@ -640,8 +643,11 @@ static int mei_txe_fw_status(struct mei_device *dev,
fw_status->count = fw_src->count; fw_status->count = fw_src->count;
for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
ret = pci_read_config_dword(pdev, ret = pci_read_config_dword(pdev, fw_src->status[i],
fw_src->status[i], &fw_status->status[i]); &fw_status->status[i]);
trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
fw_src->status[i],
fw_status->status[i]);
if (ret) if (ret)
return ret; return ret;
} }

2
drivers/misc/mei/mei-trace.c
View file

@ -22,4 +22,6 @@
EXPORT_TRACEPOINT_SYMBOL(mei_reg_read); EXPORT_TRACEPOINT_SYMBOL(mei_reg_read);
EXPORT_TRACEPOINT_SYMBOL(mei_reg_write); EXPORT_TRACEPOINT_SYMBOL(mei_reg_write);
EXPORT_TRACEPOINT_SYMBOL(mei_pci_cfg_read);
EXPORT_TRACEPOINT_SYMBOL(mei_pci_cfg_write);
#endif /* __CHECKER__ */ #endif /* __CHECKER__ */

38
drivers/misc/mei/mei-trace.h
View file

@ -64,6 +64,44 @@ TRACE_EVENT(mei_reg_write,
__get_str(dev), __entry->reg, __entry->offs, __entry->val) __get_str(dev), __entry->reg, __entry->offs, __entry->val)
); );
TRACE_EVENT(mei_pci_cfg_read,
TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
TP_ARGS(dev, reg, offs, val),
TP_STRUCT__entry(
__string(dev, dev_name(dev))
__field(const char *, reg)
__field(u32, offs)
__field(u32, val)
),
TP_fast_assign(
__assign_str(dev, dev_name(dev))
__entry->reg = reg;
__entry->offs = offs;
__entry->val = val;
),
TP_printk("[%s] pci cfg read %s:[%#x] = %#x",
__get_str(dev), __entry->reg, __entry->offs, __entry->val)
);
TRACE_EVENT(mei_pci_cfg_write,
TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
TP_ARGS(dev, reg, offs, val),
TP_STRUCT__entry(
__string(dev, dev_name(dev))
__field(const char *, reg)
__field(u32, offs)
__field(u32, val)
),
TP_fast_assign(
__assign_str(dev, dev_name(dev))
__entry->reg = reg;
__entry->offs = offs;
__entry->val = val;
),
TP_printk("[%s] pci cfg write %s[%#x] = %#x)",
__get_str(dev), __entry->reg, __entry->offs, __entry->val)
);
#endif /* _MEI_TRACE_H_ */ #endif /* _MEI_TRACE_H_ */
/* This part must be outside protection */ /* This part must be outside protection */