dt-bindings: soc: fsl: cpm_qe: Add QMC controller
Add support for the QMC (QUICC Multichannel Controller) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20230217145645.1768659-6-herve.codina@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Herve Codina
Mark Brown
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
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maintainers:
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- Herve Codina <herve.codina@bootlin.com>
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description:
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The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
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serial controller using the same TDM physical interface routed from TSA.
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properties:
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compatible:
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items:
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- enum:
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- fsl,mpc885-scc-qmc
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- fsl,mpc866-scc-qmc
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- const: fsl,cpm1-scc-qmc
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reg:
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items:
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- description: SCC (Serial communication controller) register base
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- description: SCC parameter ram base
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- description: Dual port ram base
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reg-names:
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items:
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- const: scc_regs
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- const: scc_pram
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- const: dpram
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interrupts:
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maxItems: 1
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description: SCC interrupt line in the CPM interrupt controller
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fsl,tsa-serial:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to TSA node
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- enum: [1, 2, 3]
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description: |
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TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these
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values)
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- 1: SCC2
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- 2: SCC3
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- 3: SCC4
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description:
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Should be a phandle/number pair. The phandle to TSA node and the TSA
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serial interface to use.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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'#fsl,chan-cells':
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$ref: /schemas/types.yaml#/definitions/uint32
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const: 1
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description:
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QMC consumers that use a phandle to QMC need to pass the channel number
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with this phandle.
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For instance "fsl,qmc-chan = <&qmc 16>;".
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patternProperties:
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'^channel@([0-9]|[1-5][0-9]|6[0-3])$':
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description:
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A channel managed by this controller
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type: object
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properties:
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reg:
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minimum: 0
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maximum: 63
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description:
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The channel number
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fsl,operational-mode:
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$ref: /schemas/types.yaml#/definitions/string
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enum: [transparent, hdlc]
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default: transparent
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description: |
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The channel operational mode
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- hdlc: The channel handles HDLC frames
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- transparent: The channel handles raw data without any processing
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fsl,reverse-data:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The bit order as seen on the channels is reversed,
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transmitting/receiving the MSB of each octet first.
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This flag is used only in 'transparent' mode.
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fsl,tx-ts-mask:
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$ref: /schemas/types.yaml#/definitions/uint64
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description:
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Channel assigned Tx time-slots within the Tx time-slots routed by the
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TSA to this cell.
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fsl,rx-ts-mask:
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$ref: /schemas/types.yaml#/definitions/uint64
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description:
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Channel assigned Rx time-slots within the Rx time-slots routed by the
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TSA to this cell.
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required:
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- reg
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- fsl,tx-ts-mask
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- fsl,rx-ts-mask
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- fsl,tsa-serial
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- '#address-cells'
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- '#size-cells'
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- '#fsl,chan-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/soc/cpm1-fsl,tsa.h>
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qmc@a60 {
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compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
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reg = <0xa60 0x20>,
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<0x3f00 0xc0>,
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<0x2000 0x1000>;
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reg-names = "scc_regs", "scc_pram", "dpram";
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interrupts = <27>;
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interrupt-parent = <&CPM_PIC>;
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#address-cells = <1>;
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#size-cells = <0>;
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#fsl,chan-cells = <1>;
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fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;
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channel@16 {
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/* Ch16 : First 4 even TS from all routed from TSA */
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reg = <16>;
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fsl,mode = "transparent";
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fsl,reverse-data;
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fsl,tx-ts-mask = <0x00000000 0x000000aa>;
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fsl,rx-ts-mask = <0x00000000 0x000000aa>;
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};
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channel@17 {
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/* Ch17 : First 4 odd TS from all routed from TSA */
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reg = <17>;
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fsl,mode = "transparent";
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fsl,reverse-data;
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fsl,tx-ts-mask = <0x00000000 0x00000055>;
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fsl,rx-ts-mask = <0x00000000 0x00000055>;
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};
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channel@19 {
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/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
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reg = <19>;
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fsl,mode = "hdlc";
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fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
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fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
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};
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};
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