drm/amd/display: Add more checks for exiting idle in DC
[Why] Any interface that touches registers needs to wake up the system. [How] Add a new interface dc_exit_ips_for_hw_access that wraps the check for IPS support and insert it into the public DC interfaces that touch registers. We don't re-enter, since we expect that the enter/exit to have been done on the DM side. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
Alex Deucher
parent
db8391479f
commit
a9b1a4f684
4 changed files with 63 additions and 0 deletions
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@ -417,6 +417,8 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
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if (!memcmp(&stream->adjust, adjust, sizeof(*adjust)))
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return true;
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dc_exit_ips_for_hw_access(dc);
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stream->adjust.v_total_max = adjust->v_total_max;
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stream->adjust.v_total_mid = adjust->v_total_mid;
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stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
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@ -457,6 +459,8 @@ bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
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int i = 0;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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@ -487,6 +491,8 @@ bool dc_stream_get_crtc_position(struct dc *dc,
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bool ret = false;
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struct crtc_position position;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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struct pipe_ctx *pipe =
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&dc->current_state->res_ctx.pipe_ctx[i];
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@ -606,6 +612,8 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
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if (pipe == NULL)
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return false;
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dc_exit_ips_for_hw_access(dc);
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/* By default, capture the full frame */
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param.windowa_x_start = 0;
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param.windowa_y_start = 0;
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@ -665,6 +673,8 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
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struct pipe_ctx *pipe;
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struct timing_generator *tg;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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if (pipe->stream == stream)
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@ -689,6 +699,8 @@ void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
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int i;
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struct pipe_ctx *pipe_ctx;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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if (dc->current_state->res_ctx.pipe_ctx[i].stream
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== stream) {
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@ -724,6 +736,8 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream,
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if (option > DITHER_OPTION_MAX)
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return;
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dc_exit_ips_for_hw_access(stream->ctx->dc);
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stream->dither_option = option;
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memset(¶ms, 0, sizeof(params));
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@ -748,6 +762,8 @@ bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stre
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bool ret = false;
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struct pipe_ctx *pipes;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
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pipes = &dc->current_state->res_ctx.pipe_ctx[i];
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@ -765,6 +781,8 @@ bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
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bool ret = false;
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struct pipe_ctx *pipes;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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if (dc->current_state->res_ctx.pipe_ctx[i].stream
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== stream) {
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@ -791,6 +809,8 @@ void dc_stream_set_static_screen_params(struct dc *dc,
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struct pipe_ctx *pipes_affected[MAX_PIPES];
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int num_pipes_affected = 0;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < num_streams; i++) {
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struct dc_stream_state *stream = streams[i];
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@ -1769,6 +1789,8 @@ void dc_enable_stereo(
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int i, j;
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struct pipe_ctx *pipe;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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if (context != NULL) {
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pipe = &context->res_ctx.pipe_ctx[i];
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@ -1788,6 +1810,8 @@ void dc_enable_stereo(
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void dc_trigger_sync(struct dc *dc, struct dc_state *context)
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{
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if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
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dc_exit_ips_for_hw_access(dc);
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enable_timing_multisync(dc, context);
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program_timing_sync(dc, context);
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}
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@ -2044,6 +2068,8 @@ enum dc_status dc_commit_streams(struct dc *dc,
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if (!streams_changed(dc, streams, stream_count))
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return res;
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dc_exit_ips_for_hw_access(dc);
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DC_LOG_DC("%s: %d streams\n", __func__, stream_count);
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for (i = 0; i < stream_count; i++) {
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@ -3373,6 +3399,8 @@ static void commit_planes_for_stream_fast(struct dc *dc,
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int i, j;
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struct pipe_ctx *top_pipe_to_program = NULL;
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struct dc_stream_status *stream_status = NULL;
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dc_exit_ips_for_hw_access(dc);
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dc_z10_restore(dc);
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top_pipe_to_program = resource_get_otg_master_for_stream(
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@ -3527,6 +3555,8 @@ static void commit_planes_for_stream(struct dc *dc,
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// dc->current_state anymore, so we have to cache it before we apply
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// the new SubVP context
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subvp_prev_use = false;
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dc_exit_ips_for_hw_access(dc);
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dc_z10_restore(dc);
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if (update_type == UPDATE_TYPE_FULL)
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wait_for_outstanding_hw_updates(dc, context);
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@ -4409,6 +4439,8 @@ bool dc_update_planes_and_stream(struct dc *dc,
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bool is_plane_addition = 0;
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bool is_fast_update_only;
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dc_exit_ips_for_hw_access(dc);
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populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
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is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,
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surface_count, stream_update, stream);
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@ -4529,6 +4561,8 @@ void dc_commit_updates_for_stream(struct dc *dc,
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int i, j;
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struct dc_fast_update fast_update[MAX_SURFACES] = {0};
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dc_exit_ips_for_hw_access(dc);
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populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
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stream_status = dc_stream_get_status(stream);
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context = dc->current_state;
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@ -4713,6 +4747,8 @@ void dc_set_power_state(
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case DC_ACPI_CM_POWER_STATE_D0:
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dc_state_construct(dc, dc->current_state);
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dc_exit_ips_for_hw_access(dc);
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dc_z10_restore(dc);
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dc->hwss.init_hw(dc);
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@ -4854,6 +4890,12 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
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dc->idle_optimizations_allowed = allow;
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}
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void dc_exit_ips_for_hw_access(struct dc *dc)
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{
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if (dc->caps.ips_support)
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dc_allow_idle_optimizations(dc, false);
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}
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bool dc_dmub_is_ips_idle_state(struct dc *dc)
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{
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uint32_t idle_state = 0;
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@ -423,6 +423,8 @@ bool dc_stream_add_writeback(struct dc *dc,
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return false;
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}
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dc_exit_ips_for_hw_access(dc);
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wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
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dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
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@ -493,6 +495,8 @@ bool dc_stream_fc_disable_writeback(struct dc *dc,
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return false;
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}
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dc_exit_ips_for_hw_access(dc);
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if (dwb->funcs->set_fc_enable)
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dwb->funcs->set_fc_enable(dwb, DWB_FRAME_CAPTURE_DISABLE);
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@ -542,6 +546,8 @@ bool dc_stream_remove_writeback(struct dc *dc,
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return false;
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}
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dc_exit_ips_for_hw_access(dc);
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/* disable writeback */
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if (dc->hwss.disable_writeback) {
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struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];
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@ -557,6 +563,8 @@ bool dc_stream_warmup_writeback(struct dc *dc,
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int num_dwb,
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struct dc_writeback_info *wb_info)
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{
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dc_exit_ips_for_hw_access(dc);
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if (dc->hwss.mmhubbub_warmup)
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return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
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else
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@ -569,6 +577,8 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
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struct resource_context *res_ctx =
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&dc->current_state->res_ctx;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
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@ -597,6 +607,8 @@ bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
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dc = stream->ctx->dc;
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res_ctx = &dc->current_state->res_ctx;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
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@ -628,6 +640,8 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
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struct resource_context *res_ctx =
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&dc->current_state->res_ctx;
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < MAX_PIPES; i++) {
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struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
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@ -664,6 +678,8 @@ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
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if (i == MAX_PIPES)
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return true;
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dc_exit_ips_for_hw_access(dc);
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return dc->hwss.dmdata_status_done(pipe);
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}
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@ -698,6 +714,8 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
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pipe_ctx->stream->dmdata_address = attr->address;
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dc_exit_ips_for_hw_access(dc);
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dc->hwss.program_dmdata_engine(pipe_ctx);
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if (hubp->funcs->dmdata_set_attributes != NULL &&
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@ -161,6 +161,8 @@ const struct dc_plane_status *dc_plane_get_status(
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break;
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}
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dc_exit_ips_for_hw_access(dc);
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx =
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&dc->current_state->res_ctx.pipe_ctx[i];
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@ -2325,6 +2325,7 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_
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struct dc_cursor_attributes *cursor_attr);
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void dc_allow_idle_optimizations(struct dc *dc, bool allow);
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void dc_exit_ips_for_hw_access(struct dc *dc);
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bool dc_dmub_is_ips_idle_state(struct dc *dc);
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/* set min and max memory clock to lowest and highest DPM level, respectively */
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