KVM: selftests: aarch64: vPMU register test for implemented counters
Add a new test case to the vpmu_counter_access test to check if PMU registers or their bits for implemented counters on the vCPU are readable/writable as expected, and can be programmed to count events. Signed-off-by: Reiji Watanabe <reijiw@google.com> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231020214053.2144305-11-rananta@google.com Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Reiji Watanabe
Oliver Upton
parent
8d0aebe1ca
commit
ada1ae6826
1 changed files with 266 additions and 4 deletions
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@ -5,7 +5,8 @@
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* Copyright (c) 2023 Google LLC.
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*
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* This test checks if the guest can see the same number of the PMU event
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* counters (PMCR_EL0.N) that userspace sets.
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* counters (PMCR_EL0.N) that userspace sets, and if the guest can access
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* those counters.
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* This test runs only when KVM_CAP_ARM_PMU_V3 is supported on the host.
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*/
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#include <kvm_util.h>
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@ -37,6 +38,255 @@ static void set_pmcr_n(uint64_t *pmcr, uint64_t pmcr_n)
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*pmcr |= (pmcr_n << ARMV8_PMU_PMCR_N_SHIFT);
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}
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/* Read PMEVTCNTR<n>_EL0 through PMXEVCNTR_EL0 */
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static inline unsigned long read_sel_evcntr(int sel)
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{
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write_sysreg(sel, pmselr_el0);
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isb();
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return read_sysreg(pmxevcntr_el0);
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}
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/* Write PMEVTCNTR<n>_EL0 through PMXEVCNTR_EL0 */
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static inline void write_sel_evcntr(int sel, unsigned long val)
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{
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write_sysreg(sel, pmselr_el0);
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isb();
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write_sysreg(val, pmxevcntr_el0);
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isb();
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}
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/* Read PMEVTYPER<n>_EL0 through PMXEVTYPER_EL0 */
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static inline unsigned long read_sel_evtyper(int sel)
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{
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write_sysreg(sel, pmselr_el0);
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isb();
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return read_sysreg(pmxevtyper_el0);
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}
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/* Write PMEVTYPER<n>_EL0 through PMXEVTYPER_EL0 */
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static inline void write_sel_evtyper(int sel, unsigned long val)
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{
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write_sysreg(sel, pmselr_el0);
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isb();
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write_sysreg(val, pmxevtyper_el0);
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isb();
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}
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static inline void enable_counter(int idx)
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{
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uint64_t v = read_sysreg(pmcntenset_el0);
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write_sysreg(BIT(idx) | v, pmcntenset_el0);
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isb();
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}
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static inline void disable_counter(int idx)
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{
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uint64_t v = read_sysreg(pmcntenset_el0);
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write_sysreg(BIT(idx) | v, pmcntenclr_el0);
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isb();
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}
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static void pmu_disable_reset(void)
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{
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uint64_t pmcr = read_sysreg(pmcr_el0);
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/* Reset all counters, disabling them */
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pmcr &= ~ARMV8_PMU_PMCR_E;
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write_sysreg(pmcr | ARMV8_PMU_PMCR_P, pmcr_el0);
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isb();
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}
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#define RETURN_READ_PMEVCNTRN(n) \
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return read_sysreg(pmevcntr##n##_el0)
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static unsigned long read_pmevcntrn(int n)
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{
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PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
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return 0;
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}
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#define WRITE_PMEVCNTRN(n) \
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write_sysreg(val, pmevcntr##n##_el0)
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static void write_pmevcntrn(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
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isb();
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}
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#define READ_PMEVTYPERN(n) \
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return read_sysreg(pmevtyper##n##_el0)
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static unsigned long read_pmevtypern(int n)
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{
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PMEVN_SWITCH(n, READ_PMEVTYPERN);
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return 0;
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}
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#define WRITE_PMEVTYPERN(n) \
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write_sysreg(val, pmevtyper##n##_el0)
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static void write_pmevtypern(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
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isb();
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}
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/*
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* The pmc_accessor structure has pointers to PMEV{CNTR,TYPER}<n>_EL0
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* accessors that test cases will use. Each of the accessors will
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* either directly reads/writes PMEV{CNTR,TYPER}<n>_EL0
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* (i.e. {read,write}_pmev{cnt,type}rn()), or reads/writes them through
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* PMXEV{CNTR,TYPER}_EL0 (i.e. {read,write}_sel_ev{cnt,type}r()).
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*
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* This is used to test that combinations of those accessors provide
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* the consistent behavior.
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*/
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struct pmc_accessor {
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/* A function to be used to read PMEVTCNTR<n>_EL0 */
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unsigned long (*read_cntr)(int idx);
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/* A function to be used to write PMEVTCNTR<n>_EL0 */
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void (*write_cntr)(int idx, unsigned long val);
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/* A function to be used to read PMEVTYPER<n>_EL0 */
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unsigned long (*read_typer)(int idx);
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/* A function to be used to write PMEVTYPER<n>_EL0 */
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void (*write_typer)(int idx, unsigned long val);
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};
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struct pmc_accessor pmc_accessors[] = {
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/* test with all direct accesses */
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{ read_pmevcntrn, write_pmevcntrn, read_pmevtypern, write_pmevtypern },
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/* test with all indirect accesses */
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{ read_sel_evcntr, write_sel_evcntr, read_sel_evtyper, write_sel_evtyper },
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/* read with direct accesses, and write with indirect accesses */
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{ read_pmevcntrn, write_sel_evcntr, read_pmevtypern, write_sel_evtyper },
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/* read with indirect accesses, and write with direct accesses */
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{ read_sel_evcntr, write_pmevcntrn, read_sel_evtyper, write_pmevtypern },
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};
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/*
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* Convert a pointer of pmc_accessor to an index in pmc_accessors[],
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* assuming that the pointer is one of the entries in pmc_accessors[].
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*/
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#define PMC_ACC_TO_IDX(acc) (acc - &pmc_accessors[0])
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#define GUEST_ASSERT_BITMAP_REG(regname, mask, set_expected) \
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{ \
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uint64_t _tval = read_sysreg(regname); \
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\
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if (set_expected) \
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__GUEST_ASSERT((_tval & mask), \
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"tval: 0x%lx; mask: 0x%lx; set_expected: 0x%lx", \
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_tval, mask, set_expected); \
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else \
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__GUEST_ASSERT(!(_tval & mask), \
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"tval: 0x%lx; mask: 0x%lx; set_expected: 0x%lx", \
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_tval, mask, set_expected); \
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}
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/*
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* Check if @mask bits in {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers
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* are set or cleared as specified in @set_expected.
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*/
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static void check_bitmap_pmu_regs(uint64_t mask, bool set_expected)
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{
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GUEST_ASSERT_BITMAP_REG(pmcntenset_el0, mask, set_expected);
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GUEST_ASSERT_BITMAP_REG(pmcntenclr_el0, mask, set_expected);
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GUEST_ASSERT_BITMAP_REG(pmintenset_el1, mask, set_expected);
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GUEST_ASSERT_BITMAP_REG(pmintenclr_el1, mask, set_expected);
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GUEST_ASSERT_BITMAP_REG(pmovsset_el0, mask, set_expected);
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GUEST_ASSERT_BITMAP_REG(pmovsclr_el0, mask, set_expected);
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}
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/*
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* Check if the bit in {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers corresponding
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* to the specified counter (@pmc_idx) can be read/written as expected.
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* When @set_op is true, it tries to set the bit for the counter in
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* those registers by writing the SET registers (the bit won't be set
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* if the counter is not implemented though).
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* Otherwise, it tries to clear the bits in the registers by writing
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* the CLR registers.
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* Then, it checks if the values indicated in the registers are as expected.
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*/
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static void test_bitmap_pmu_regs(int pmc_idx, bool set_op)
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{
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uint64_t pmcr_n, test_bit = BIT(pmc_idx);
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bool set_expected = false;
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if (set_op) {
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write_sysreg(test_bit, pmcntenset_el0);
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write_sysreg(test_bit, pmintenset_el1);
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write_sysreg(test_bit, pmovsset_el0);
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/* The bit will be set only if the counter is implemented */
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pmcr_n = get_pmcr_n(read_sysreg(pmcr_el0));
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set_expected = (pmc_idx < pmcr_n) ? true : false;
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} else {
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write_sysreg(test_bit, pmcntenclr_el0);
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write_sysreg(test_bit, pmintenclr_el1);
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write_sysreg(test_bit, pmovsclr_el0);
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}
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check_bitmap_pmu_regs(test_bit, set_expected);
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}
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/*
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* Tests for reading/writing registers for the (implemented) event counter
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* specified by @pmc_idx.
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*/
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static void test_access_pmc_regs(struct pmc_accessor *acc, int pmc_idx)
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{
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uint64_t write_data, read_data;
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/* Disable all PMCs and reset all PMCs to zero. */
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pmu_disable_reset();
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/*
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* Tests for reading/writing {PMCNTEN,PMINTEN,PMOVS}{SET,CLR}_EL1.
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*/
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/* Make sure that the bit in those registers are set to 0 */
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test_bitmap_pmu_regs(pmc_idx, false);
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/* Test if setting the bit in those registers works */
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test_bitmap_pmu_regs(pmc_idx, true);
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/* Test if clearing the bit in those registers works */
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test_bitmap_pmu_regs(pmc_idx, false);
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/*
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* Tests for reading/writing the event type register.
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*/
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/*
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* Set the event type register to an arbitrary value just for testing
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* of reading/writing the register.
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* Arm ARM says that for the event from 0x0000 to 0x003F,
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* the value indicated in the PMEVTYPER<n>_EL0.evtCount field is
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* the value written to the field even when the specified event
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* is not supported.
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*/
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write_data = (ARMV8_PMU_EXCLUDE_EL1 | ARMV8_PMUV3_PERFCTR_INST_RETIRED);
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acc->write_typer(pmc_idx, write_data);
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read_data = acc->read_typer(pmc_idx);
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__GUEST_ASSERT(read_data == write_data,
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"pmc_idx: 0x%lx; acc_idx: 0x%lx; read_data: 0x%lx; write_data: 0x%lx",
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pmc_idx, PMC_ACC_TO_IDX(acc), read_data, write_data);
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/*
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* Tests for reading/writing the event count register.
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*/
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read_data = acc->read_cntr(pmc_idx);
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/* The count value must be 0, as it is disabled and reset */
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__GUEST_ASSERT(read_data == 0,
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"pmc_idx: 0x%lx; acc_idx: 0x%lx; read_data: 0x%lx",
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pmc_idx, PMC_ACC_TO_IDX(acc), read_data);
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write_data = read_data + pmc_idx + 0x12345;
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acc->write_cntr(pmc_idx, write_data);
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read_data = acc->read_cntr(pmc_idx);
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__GUEST_ASSERT(read_data == write_data,
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"pmc_idx: 0x%lx; acc_idx: 0x%lx; read_data: 0x%lx; write_data: 0x%lx",
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pmc_idx, PMC_ACC_TO_IDX(acc), read_data, write_data);
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}
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static void guest_sync_handler(struct ex_regs *regs)
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{
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uint64_t esr, ec;
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@ -49,11 +299,14 @@ static void guest_sync_handler(struct ex_regs *regs)
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/*
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* The guest is configured with PMUv3 with @expected_pmcr_n number of
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* event counters.
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* Check if @expected_pmcr_n is consistent with PMCR_EL0.N.
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* Check if @expected_pmcr_n is consistent with PMCR_EL0.N, and
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* if reading/writing PMU registers for implemented counters works
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* as expected.
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*/
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static void guest_code(uint64_t expected_pmcr_n)
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{
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uint64_t pmcr, pmcr_n;
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int i, pmc;
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__GUEST_ASSERT(expected_pmcr_n <= ARMV8_PMU_MAX_GENERAL_COUNTERS,
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"Expected PMCR.N: 0x%lx; ARMv8 general counters: 0x%lx",
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@ -67,6 +320,15 @@ static void guest_code(uint64_t expected_pmcr_n)
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"Expected PMCR.N: 0x%lx, PMCR.N: 0x%lx",
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expected_pmcr_n, pmcr_n);
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/*
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* Tests for reading/writing PMU registers for implemented counters.
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* Use each combination of PMEVT{CNTR,TYPER}<n>_EL0 accessor functions.
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*/
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for (i = 0; i < ARRAY_SIZE(pmc_accessors); i++) {
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for (pmc = 0; pmc < pmcr_n; pmc++)
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test_access_pmc_regs(&pmc_accessors[i], pmc);
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}
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GUEST_DONE();
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}
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@ -179,7 +441,7 @@ static void test_create_vpmu_vm_with_pmcr_n(uint64_t pmcr_n, bool expect_fail)
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* Create a guest with one vCPU, set the PMCR_EL0.N for the vCPU to @pmcr_n,
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* and run the test.
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*/
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static void run_test(uint64_t pmcr_n)
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static void run_access_test(uint64_t pmcr_n)
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{
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uint64_t sp;
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struct kvm_vcpu *vcpu;
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@ -246,7 +508,7 @@ int main(void)
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pmcr_n = get_pmcr_n_limit();
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for (i = 0; i <= pmcr_n; i++)
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run_test(i);
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run_access_test(i);
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for (i = pmcr_n + 1; i < ARMV8_PMU_MAX_COUNTERS; i++)
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run_error_test(i);
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