drm/amd/display: Correcting prefetch mode for fast validate
[WHY and HOW] When fast validating, we should be agnostic to any sort of optimizations such as supporting Pstate or stutter in Vblank. We should change our prefetch mode for fast validate to support none of these optimizations. For example, Valve Index running at 144Hz can only be validated without any support these optimizations. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 1 additions and 7 deletions
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@ -1601,17 +1601,11 @@ bool dcn32_internal_validate_bw(struct dc *dc,
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* to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)
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*/
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context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
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dm_prefetch_support_fclk_and_stutter;
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dm_prefetch_support_none;
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context->bw_ctx.dml.validate_max_state = fast_validate;
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vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
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/* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */
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if (vlevel == context->bw_ctx.dml.soc.num_states) {
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context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
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dm_prefetch_support_stutter;
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vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
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}
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context->bw_ctx.dml.validate_max_state = false;
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if (vlevel < context->bw_ctx.dml.soc.num_states) {
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