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ARM: dts: Group omap3 CM_CLKSEL_CORE clocks

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The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.

With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2022-04-29 09:57:36 +03:00
parent 4e28ab96e3
commit b0985e0278
3 changed files with 78 additions and 56 deletions
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41
arch/arm/boot/dts/omap3430es1-clocks.dtsi
View file

@ -77,13 +77,30 @@
}; };
}; };
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { clock@a40 {
#clock-cells = <0>; compatible = "ti,clksel";
compatible = "ti,composite-divider-clock"; reg = <0xa40>;
clocks = <&corex2_fck>; #clock-cells = <2>;
ti,bit-shift = <8>; #address-cells = <0>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "ssi_ssr_div_fck_3430es1";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
usb_l4_div_ick: clock-usb-l4-div-ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "usb_l4_div_ick";
clocks = <&l4_ick>;
ti,bit-shift = <4>;
ti,max-div = <1>;
ti,index-starts-at-one;
};
}; };
ssi_ssr_fck: ssi_ssr_fck_3430es1 { ssi_ssr_fck: ssi_ssr_fck_3430es1 {
@ -147,16 +164,6 @@
clock-div = <1>; clock-div = <1>;
}; };
usb_l4_div_ick: usb_l4_div_ick@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&l4_ick>;
ti,bit-shift = <4>;
ti,max-div = <1>;
reg = <0x0a40>;
ti,index-starts-at-one;
};
usb_l4_ick: usb_l4_ick { usb_l4_ick: usb_l4_ick {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,composite-clock"; compatible = "ti,composite-clock";

21
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
View file

@ -20,13 +20,20 @@
}; };
}; };
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { clock@a40 {
#clock-cells = <0>; compatible = "ti,clksel";
compatible = "ti,composite-divider-clock"; reg = <0xa40>;
clocks = <&corex2_fck>; #clock-cells = <2>;
ti,bit-shift = <8>; #address-cells = <0>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "ssi_ssr_div_fck_3430es2";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
}; };
ssi_ssr_fck: ssi_ssr_fck_3430es2 { ssi_ssr_fck: ssi_ssr_fck_3430es2 {

72
arch/arm/boot/dts/omap3xxx-clocks.dtsi
View file

@ -574,23 +574,47 @@
clock-div = <1>; clock-div = <1>;
}; };
l3_ick: l3_ick@a40 { /* CM_CLKSEL_CORE */
#clock-cells = <0>; clock@a40 {
compatible = "ti,divider-clock"; compatible = "ti,clksel";
clocks = <&core_ck>; reg = <0xa40>;
ti,max-div = <3>; #clock-cells = <2>;
reg = <0x0a40>; #address-cells = <0>;
ti,index-starts-at-one;
};
l4_ick: l4_ick@a40 { l3_ick: clock-l3-ick {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,divider-clock"; compatible = "ti,divider-clock";
clocks = <&l3_ick>; clock-output-names = "l3_ick";
ti,bit-shift = <2>; clocks = <&core_ck>;
ti,max-div = <3>; ti,max-div = <3>;
reg = <0x0a40>; ti,index-starts-at-one;
ti,index-starts-at-one; };
l4_ick: clock-l4-ick {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "l4_ick";
clocks = <&l3_ick>;
ti,bit-shift = <2>;
ti,max-div = <3>;
ti,index-starts-at-one;
};
gpt10_mux_fck: clock-gpt10-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt10_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <6>;
};
gpt11_mux_fck: clock-gpt11-mux-fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt11_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <7>;
};
}; };
rm_ick: rm_ick@c40 { rm_ick: rm_ick@c40 {
@ -739,28 +763,12 @@
}; };
}; };
gpt10_mux_fck: gpt10_mux_fck@a40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <6>;
reg = <0x0a40>;
};
gpt10_fck: gpt10_fck { gpt10_fck: gpt10_fck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,composite-clock"; compatible = "ti,composite-clock";
clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
}; };
gpt11_mux_fck: gpt11_mux_fck@a40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
ti,bit-shift = <7>;
reg = <0x0a40>;
};
gpt11_fck: gpt11_fck { gpt11_fck: gpt11_fck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,composite-clock"; compatible = "ti,composite-clock";