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pinctrl: amd: Disable and mask interrupts on resume

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This fixes a similar problem to the one observed in:
commit 4e5a04be88 ("pinctrl: amd: disable and mask interrupts on probe").

On some systems, during suspend/resume cycle firmware leaves
an interrupt enabled on a pin that is not used by the kernel.
This confuses the AMD pinctrl driver and causes spurious interrupts.

The driver already has logic to detect if a pin is used by the kernel.
Leverage it to re-initialize interrupt fields of a pin only if it's not
used by us.

Cc: stable@vger.kernel.org
Fixes: dbad75dd1f ("pinctrl: add AMD GPIO driver support.")
Signed-off-by: Kornel Dulęba <korneld@chromium.org>
Link: https://lore.kernel.org/r/20230320093259.845178-1-korneld@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Kornel Dulęba 2023-03-20 09:32:59 +00:00 • committed by Linus Walleij
parent 913a956c43
commit b26cd9325b
1 changed files with 20 additions and 16 deletions
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32
drivers/pinctrl/pinctrl-amd.c
View file

@ -872,32 +872,34 @@ static const struct pinconf_ops amd_pinconf_ops = {
.pin_config_group_set = amd_pinconf_group_set, .pin_config_group_set = amd_pinconf_group_set,
}; };
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin)
{ {
struct pinctrl_desc *desc = gpio_dev->pctrl->desc; const struct pin_desc *pd;
unsigned long flags; unsigned long flags;
u32 pin_reg, mask; u32 pin_reg, mask;
int i;
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
BIT(WAKE_CNTRL_OFF_S4); BIT(WAKE_CNTRL_OFF_S4);
for (i = 0; i < desc->npins; i++) { pd = pin_desc_get(gpio_dev->pctrl, pin);
int pin = desc->pins[i].number;
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
if (!pd) if (!pd)
continue; return;
raw_spin_lock_irqsave(&gpio_dev->lock, flags); raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + pin * 4);
pin_reg = readl(gpio_dev->base + i * 4);
pin_reg &= ~mask; pin_reg &= ~mask;
writel(pin_reg, gpio_dev->base + i * 4); writel(pin_reg, gpio_dev->base + pin * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
} }
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
{
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;
for (i = 0; i < desc->npins; i++)
amd_gpio_irq_init_pin(gpio_dev, i);
} }
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
@ -950,8 +952,10 @@ static int amd_gpio_resume(struct device *dev)
for (i = 0; i < desc->npins; i++) { for (i = 0; i < desc->npins; i++) {
int pin = desc->pins[i].number; int pin = desc->pins[i].number;
if (!amd_gpio_should_save(gpio_dev, pin)) if (!amd_gpio_should_save(gpio_dev, pin)) {
amd_gpio_irq_init_pin(gpio_dev, pin);
continue; continue;
}
raw_spin_lock_irqsave(&gpio_dev->lock, flags); raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;