drm/amd/display: Only blank DCN when we have set_blank implementation
Also rename timing_generator to optc Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7 changed files with 32 additions and 31 deletions
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@ -23,7 +23,7 @@
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# Makefile for DCN.
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DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
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dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
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dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
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dcn10_hubp.o dcn10_mpc.o \
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dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
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dcn10_hubbub.o
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@ -32,7 +32,7 @@
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#include "dce/dce_hwseq.h"
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#include "abm.h"
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#include "dmcu.h"
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#include "dcn10/dcn10_timing_generator.h"
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#include "dcn10_optc.h"
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#include "dcn10/dcn10_dpp.h"
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#include "dcn10/dcn10_mpc.h"
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#include "timing_generator.h"
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@ -465,6 +465,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
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bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
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false:true;
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bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
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int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
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int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
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/* by upper caller loop, pipe0 is parent pipe and be called first.
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* back end is set up by for pipe0. Other children pipe share back end
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@ -518,11 +520,14 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
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/* program otg blank color */
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color_space = stream->output_color_space;
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color_space_to_black_color(dc, color_space, &black_color);
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pipe_ctx->stream_res.tg->funcs->set_blank_color(
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pipe_ctx->stream_res.tg,
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&black_color);
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if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
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if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
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pipe_ctx->stream_res.tg->funcs->set_blank_color(
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pipe_ctx->stream_res.tg,
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&black_color);
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if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
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!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
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pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
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hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
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false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
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@ -1808,6 +1813,10 @@ static void program_all_pipe_in_tree(
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struct pipe_ctx *pipe_ctx,
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struct dc_state *context)
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{
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struct dc_stream_state *stream = pipe_ctx->stream;
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int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
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int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
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if (pipe_ctx->top_pipe == NULL) {
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pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
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@ -1818,7 +1827,11 @@ static void program_all_pipe_in_tree(
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pipe_ctx->stream_res.tg->funcs->program_global_sync(
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pipe_ctx->stream_res.tg);
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pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
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if (pipe_ctx->stream_res.tg->funcs->set_blank)
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pipe_ctx->stream_res.tg->funcs->set_blank(
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pipe_ctx->stream_res.tg,
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!is_pipe_tree_visible(pipe_ctx));
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}
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if (pipe_ctx->plane_state != NULL) {
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@ -1925,9 +1938,12 @@ static void dcn10_apply_ctx_for_surface(
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{
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int i;
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struct timing_generator *tg;
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struct output_pixel_processor *opp;
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bool removed_pipe[4] = { false };
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unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
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bool program_water_mark = false;
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int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
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int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
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struct pipe_ctx *top_pipe_to_program =
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find_top_pipe_for_stream(dc, context, stream);
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@ -1935,6 +1951,8 @@ static void dcn10_apply_ctx_for_surface(
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if (!top_pipe_to_program)
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return;
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opp = top_pipe_to_program->stream_res.opp;
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tg = top_pipe_to_program->stream_res.tg;
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tg->funcs->lock(tg);
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@ -1942,7 +1960,8 @@ static void dcn10_apply_ctx_for_surface(
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if (num_planes == 0) {
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/* OTG blank before remove all front end */
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tg->funcs->set_blank(tg, true);
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if (tg->funcs->set_blank)
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tg->funcs->set_blank(tg, true);
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}
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/* Disconnect unused mpcc */
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@ -23,8 +23,9 @@
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*
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*/
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#include "reg_helper.h"
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#include "dcn10_timing_generator.h"
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#include "dcn10_optc.h"
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#include "dc.h"
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#define REG(reg)\
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@ -251,8 +252,7 @@ void optc1_program_timing(
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v_init = v_init / 2;
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if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
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v_fp2 = v_fp2 / 2;
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}
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else
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} else
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REG_UPDATE(OTG_INTERLACE_CONTROL,
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OTG_INTERLACE_ENABLE, 0);
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@ -34,7 +34,7 @@
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#include "dcn10/dcn10_mpc.h"
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#include "irq/dcn10/irq_service_dcn10.h"
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#include "dcn10/dcn10_dpp.h"
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#include "dcn10/dcn10_timing_generator.h"
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#include "dcn10_optc.h"
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#include "dcn10/dcn10_hw_sequencer.h"
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#include "dce110/dce110_hw_sequencer.h"
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#include "dcn10/dcn10_opp.h"
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@ -282,25 +282,6 @@ struct opp_funcs {
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bool enable,
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bool rightEyePolarity);
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void (*opp_set_test_pattern)(
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struct output_pixel_processor *opp,
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enum controller_dp_test_pattern test_pattern,
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enum dc_color_depth color_depth,
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int width,
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int height);
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void (*opp_dpg_blank_enable)(
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struct output_pixel_processor *opp,
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bool enable,
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const struct tg_color *color,
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int width,
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int height);
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void (*opp_convert_pti)(
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struct output_pixel_processor *opp,
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bool enable,
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bool polarity);
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};
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#endif
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@ -28,6 +28,7 @@
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#include "dc_types.h"
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#include "clock_source.h"
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#include "inc/hw/timing_generator.h"
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#include "inc/hw/opp.h"
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#include "inc/hw/link_encoder.h"
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#include "core_status.h"
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