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MIPS: Make DIEI support as a config option

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DI(Disable Interrupt) and EI(Enable Interrupt) instructions is required by
MIPSR2/MIPSR6, however, it appears to be buggy on some processors such as
Loongson-3A1000. Thus we make it as a config option to allow disable it at
compile time with CPU_MIPSR2 selected.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com
Cc: paul.burton@mips.com
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Jiaxun Yang 2020-01-13 18:14:59 +08:00 • committed by Paul Burton
parent 636e9d23dd
commit ba9196d2e0
No known key found for this signature in database
GPG key ID: 3EA79FACB57500DD
3 changed files with 14 additions and 5 deletions
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9
arch/mips/Kconfig
View file

@ -2084,12 +2084,14 @@ config CPU_MIPSR2
bool bool
default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
select CPU_HAS_RIXI select CPU_HAS_RIXI
select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select MIPS_SPRAM select MIPS_SPRAM
config CPU_MIPSR6 config CPU_MIPSR6
bool bool
default y if CPU_MIPS32_R6 || CPU_MIPS64_R6 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
select CPU_HAS_RIXI select CPU_HAS_RIXI
select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select HAVE_ARCH_BITREVERSE select HAVE_ARCH_BITREVERSE
select MIPS_ASID_BITS_VARIABLE select MIPS_ASID_BITS_VARIABLE
select MIPS_CRC_SUPPORT select MIPS_CRC_SUPPORT
@ -2549,6 +2551,13 @@ config CPU_HAS_WB
config XKS01 config XKS01
bool bool
config CPU_HAS_DIEI
depends on !CPU_DIEI_BROKEN
bool
config CPU_DIEI_BROKEN
bool
config CPU_HAS_RIXI config CPU_HAS_RIXI
bool bool

6
arch/mips/include/asm/irqflags.h
View file

@ -18,7 +18,7 @@
#include <asm/compiler.h> #include <asm/compiler.h>
#include <asm/hazards.h> #include <asm/hazards.h>
#if defined(CONFIG_CPU_MIPSR2) || defined (CONFIG_CPU_MIPSR6) #if defined(CONFIG_CPU_HAS_DIEI)
static inline void arch_local_irq_disable(void) static inline void arch_local_irq_disable(void)
{ {
@ -94,7 +94,7 @@ static inline void arch_local_irq_restore(unsigned long flags)
void arch_local_irq_disable(void); void arch_local_irq_disable(void);
unsigned long arch_local_irq_save(void); unsigned long arch_local_irq_save(void);
void arch_local_irq_restore(unsigned long flags); void arch_local_irq_restore(unsigned long flags);
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */ #endif /* CONFIG_CPU_HAS_DIEI */
static inline void arch_local_irq_enable(void) static inline void arch_local_irq_enable(void)
{ {
@ -102,7 +102,7 @@ static inline void arch_local_irq_enable(void)
" .set push \n" " .set push \n"
" .set reorder \n" " .set reorder \n"
" .set noat \n" " .set noat \n"
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) #if defined(CONFIG_CPU_HAS_DIEI)
" ei \n" " ei \n"
#else #else
" mfc0 $1,$12 \n" " mfc0 $1,$12 \n"

4
arch/mips/lib/mips-atomic.c
View file

@ -15,7 +15,7 @@
#include <linux/export.h> #include <linux/export.h>
#include <linux/stringify.h> #include <linux/stringify.h>
#if !defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_MIPSR6) #if !defined(CONFIG_CPU_HAS_DIEI)
/* /*
* For cli() we have to insert nops to make sure that the new value * For cli() we have to insert nops to make sure that the new value
@ -110,4 +110,4 @@ notrace void arch_local_irq_restore(unsigned long flags)
} }
EXPORT_SYMBOL(arch_local_irq_restore); EXPORT_SYMBOL(arch_local_irq_restore);
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */ #endif /* !CONFIG_CPU_HAS_DIEI */