s390:
* fix a latent bug when the kernel is compiled in debug mode
* two small UCONTROL fixes and their selftests
arm64:
* always check page state in hyp_ack_unshare()
* align set_id_regs selftest with the fact that ASIDBITS field is RO
* various vPMU fixes for bugs that only affect nested virt
PPC e500:
* Fix a mostly impossible (but just wrong) case where IRQs were
never re-enabled
* Observe host permissions instead of mapping readonly host pages as
guest-writable. This fixes a NULL-pointer dereference in 6.13
* Replace brittle VMA-based attempts at building huge shadow TLB entries
with PTE lookups.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm fixes from Paolo Bonzini:
"The largest part here is for KVM/PPC, where a NULL pointer dereference
was introduced in the 6.13 merge window and is now fixed.
There's some "holiday-induced lateness", as the s390 submaintainer put
it, but otherwise things looks fine.
s390:
- fix a latent bug when the kernel is compiled in debug mode
- two small UCONTROL fixes and their selftests
arm64:
- always check page state in hyp_ack_unshare()
- align set_id_regs selftest with the fact that ASIDBITS field is RO
- various vPMU fixes for bugs that only affect nested virt
PPC e500:
- Fix a mostly impossible (but just wrong) case where IRQs were never
re-enabled
- Observe host permissions instead of mapping readonly host pages as
guest-writable. This fixes a NULL-pointer dereference in 6.13
- Replace brittle VMA-based attempts at building huge shadow TLB
entries with PTE lookups"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: e500: perform hugepage check after looking up the PFN
KVM: e500: map readonly host pages for read
KVM: e500: track host-writability of pages
KVM: e500: use shadow TLB entry as witness for writability
KVM: e500: always restore irqs
KVM: s390: selftests: Add has device attr check to uc_attr_mem_limit selftest
KVM: s390: selftests: Add ucontrol gis routing test
KVM: s390: Reject KVM_SET_GSI_ROUTING on ucontrol VMs
KVM: s390: selftests: Add ucontrol flic attr selftests
KVM: s390: Reject setting flic pfault attributes on ucontrol VMs
KVM: s390: vsie: fix virtual/physical address in unpin_scb()
KVM: arm64: Only apply PMCR_EL0.P to the guest range of counters
KVM: arm64: nv: Reload PMU events upon MDCR_EL2.HPME change
KVM: arm64: Use KVM_REQ_RELOAD_PMU to handle PMCR_EL0.E change
KVM: arm64: Add unified helper for reprogramming counters by mask
KVM: arm64: Always check the state from hyp_ack_unshare()
KVM: arm64: Fix set_id_regs selftest for ASIDBITS becoming unwritable
This commit is contained in:
Linus Torvalds
commit
be54864552
12 changed files with 333 additions and 188 deletions
|
|
@ -1914,6 +1914,9 @@ No flags are specified so far, the corresponding field must be set to zero.
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#define KVM_IRQ_ROUTING_HV_SINT 4
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#define KVM_IRQ_ROUTING_XEN_EVTCHN 5
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On s390, adding a KVM_IRQ_ROUTING_S390_ADAPTER is rejected on ucontrol VMs with
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error -EINVAL.
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flags:
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- KVM_MSI_VALID_DEVID: used along with KVM_IRQ_ROUTING_MSI routing entry
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|
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@ -58,11 +58,15 @@ Groups:
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Enables async page faults for the guest. So in case of a major page fault
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the host is allowed to handle this async and continues the guest.
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-EINVAL is returned when called on the FLIC of a ucontrol VM.
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KVM_DEV_FLIC_APF_DISABLE_WAIT
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Disables async page faults for the guest and waits until already pending
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async page faults are done. This is necessary to trigger a completion interrupt
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for every init interrupt before migrating the interrupt list.
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-EINVAL is returned when called on the FLIC of a ucontrol VM.
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KVM_DEV_FLIC_ADAPTER_REGISTER
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Register an I/O adapter interrupt source. Takes a kvm_s390_io_adapter
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describing the adapter to register::
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@ -783,9 +783,6 @@ static int hyp_ack_unshare(u64 addr, const struct pkvm_mem_transition *tx)
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if (tx->initiator.id == PKVM_ID_HOST && hyp_page_count((void *)addr))
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return -EBUSY;
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if (__hyp_ack_skip_pgtable_check(tx))
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return 0;
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return __hyp_check_page_state_range(addr, size,
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PKVM_PAGE_SHARED_BORROWED);
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}
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|
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@ -24,6 +24,7 @@ static DEFINE_MUTEX(arm_pmus_lock);
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static void kvm_pmu_create_perf_event(struct kvm_pmc *pmc);
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static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc);
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static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc);
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static struct kvm_vcpu *kvm_pmc_to_vcpu(const struct kvm_pmc *pmc)
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{
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@ -327,48 +328,25 @@ u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu)
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return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX);
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}
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/**
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* kvm_pmu_enable_counter_mask - enable selected PMU counters
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* @vcpu: The vcpu pointer
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* @val: the value guest writes to PMCNTENSET register
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*
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* Call perf_event_enable to start counting the perf event
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*/
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void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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static void kvm_pmc_enable_perf_event(struct kvm_pmc *pmc)
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{
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int i;
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if (!kvm_vcpu_has_pmu(vcpu))
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if (!pmc->perf_event) {
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kvm_pmu_create_perf_event(pmc);
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return;
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if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) || !val)
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return;
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for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) {
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struct kvm_pmc *pmc;
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if (!(val & BIT(i)))
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continue;
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pmc = kvm_vcpu_idx_to_pmc(vcpu, i);
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if (!pmc->perf_event) {
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kvm_pmu_create_perf_event(pmc);
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} else {
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perf_event_enable(pmc->perf_event);
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if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE)
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kvm_debug("fail to enable perf event\n");
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}
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}
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perf_event_enable(pmc->perf_event);
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if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE)
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kvm_debug("fail to enable perf event\n");
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}
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/**
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* kvm_pmu_disable_counter_mask - disable selected PMU counters
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* @vcpu: The vcpu pointer
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* @val: the value guest writes to PMCNTENCLR register
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*
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* Call perf_event_disable to stop counting the perf event
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*/
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void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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static void kvm_pmc_disable_perf_event(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event)
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perf_event_disable(pmc->perf_event);
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}
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void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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{
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int i;
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@ -376,16 +354,18 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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return;
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for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) {
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struct kvm_pmc *pmc;
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struct kvm_pmc *pmc = kvm_vcpu_idx_to_pmc(vcpu, i);
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if (!(val & BIT(i)))
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continue;
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pmc = kvm_vcpu_idx_to_pmc(vcpu, i);
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if (pmc->perf_event)
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perf_event_disable(pmc->perf_event);
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if (kvm_pmu_counter_is_enabled(pmc))
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kvm_pmc_enable_perf_event(pmc);
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else
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kvm_pmc_disable_perf_event(pmc);
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}
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kvm_vcpu_pmu_restore_guest(vcpu);
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}
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/*
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@ -626,27 +606,28 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
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if (!kvm_has_feat(vcpu->kvm, ID_AA64DFR0_EL1, PMUVer, V3P5))
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val &= ~ARMV8_PMU_PMCR_LP;
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/* Request a reload of the PMU to enable/disable affected counters */
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if ((__vcpu_sys_reg(vcpu, PMCR_EL0) ^ val) & ARMV8_PMU_PMCR_E)
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kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
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/* The reset bits don't indicate any state, and shouldn't be saved. */
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__vcpu_sys_reg(vcpu, PMCR_EL0) = val & ~(ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_P);
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if (val & ARMV8_PMU_PMCR_E) {
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kvm_pmu_enable_counter_mask(vcpu,
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__vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
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} else {
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kvm_pmu_disable_counter_mask(vcpu,
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__vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
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}
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if (val & ARMV8_PMU_PMCR_C)
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kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
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if (val & ARMV8_PMU_PMCR_P) {
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unsigned long mask = kvm_pmu_accessible_counter_mask(vcpu);
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mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
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/*
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* Unlike other PMU sysregs, the controls in PMCR_EL0 always apply
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* to the 'guest' range of counters and never the 'hyp' range.
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*/
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unsigned long mask = kvm_pmu_implemented_counter_mask(vcpu) &
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~kvm_pmu_hyp_counter_mask(vcpu) &
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~BIT(ARMV8_PMU_CYCLE_IDX);
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for_each_set_bit(i, &mask, 32)
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kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, i), 0, true);
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}
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kvm_vcpu_pmu_restore_guest(vcpu);
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}
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static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc)
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|
|
@ -910,11 +891,11 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu)
|
|||
{
|
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u64 mask = kvm_pmu_implemented_counter_mask(vcpu);
|
||||
|
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kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu));
|
||||
|
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__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask;
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__vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= mask;
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__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= mask;
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||||
kvm_pmu_reprogram_counter_mask(vcpu, mask);
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||||
}
|
||||
|
||||
int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
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||||
|
|
|
|||
|
|
@ -1208,16 +1208,14 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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|||
mask = kvm_pmu_accessible_counter_mask(vcpu);
|
||||
if (p->is_write) {
|
||||
val = p->regval & mask;
|
||||
if (r->Op2 & 0x1) {
|
||||
if (r->Op2 & 0x1)
|
||||
/* accessing PMCNTENSET_EL0 */
|
||||
__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
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kvm_pmu_enable_counter_mask(vcpu, val);
|
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kvm_vcpu_pmu_restore_guest(vcpu);
|
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} else {
|
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else
|
||||
/* accessing PMCNTENCLR_EL0 */
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__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
|
||||
kvm_pmu_disable_counter_mask(vcpu, val);
|
||||
}
|
||||
|
||||
kvm_pmu_reprogram_counter_mask(vcpu, val);
|
||||
} else {
|
||||
p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
|
||||
}
|
||||
|
|
@ -2450,6 +2448,26 @@ static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu,
|
|||
return __el2_visibility(vcpu, rd, s1pie_visibility);
|
||||
}
|
||||
|
||||
static bool access_mdcr(struct kvm_vcpu *vcpu,
|
||||
struct sys_reg_params *p,
|
||||
const struct sys_reg_desc *r)
|
||||
{
|
||||
u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2);
|
||||
|
||||
if (!access_rw(vcpu, p, r))
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Request a reload of the PMU to enable/disable the counters affected
|
||||
* by HPME.
|
||||
*/
|
||||
if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME)
|
||||
kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Architected system registers.
|
||||
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
|
||||
|
|
@ -2983,7 +3001,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
|
|||
EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
|
||||
EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
|
||||
EL2_REG_VNCR(HCR_EL2, reset_hcr, 0),
|
||||
EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
|
||||
EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0),
|
||||
EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
|
||||
EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
|
||||
EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0),
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ enum vcpu_ftr {
|
|||
#define E500_TLB_BITMAP (1 << 30)
|
||||
/* TLB1 entry is mapped by host TLB0 */
|
||||
#define E500_TLB_TLB0 (1 << 29)
|
||||
/* entry is writable on the host */
|
||||
#define E500_TLB_WRITABLE (1 << 28)
|
||||
/* bits [6-5] MAS2_X1 and MAS2_X0 and [4-0] bits for WIMGE */
|
||||
#define E500_TLB_MAS2_ATTR (0x7f)
|
||||
|
||||
|
|
|
|||
|
|
@ -45,11 +45,14 @@ static inline unsigned int tlb1_max_shadow_size(void)
|
|||
return host_tlb_params[1].entries - tlbcam_index - 1;
|
||||
}
|
||||
|
||||
static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode)
|
||||
static inline u32 e500_shadow_mas3_attrib(u32 mas3, bool writable, int usermode)
|
||||
{
|
||||
/* Mask off reserved bits. */
|
||||
mas3 &= MAS3_ATTRIB_MASK;
|
||||
|
||||
if (!writable)
|
||||
mas3 &= ~(MAS3_UW|MAS3_SW);
|
||||
|
||||
#ifndef CONFIG_KVM_BOOKE_HV
|
||||
if (!usermode) {
|
||||
/* Guest is in supervisor mode,
|
||||
|
|
@ -242,17 +245,18 @@ static inline int tlbe_is_writable(struct kvm_book3e_206_tlb_entry *tlbe)
|
|||
return tlbe->mas7_3 & (MAS3_SW|MAS3_UW);
|
||||
}
|
||||
|
||||
static inline bool kvmppc_e500_ref_setup(struct tlbe_ref *ref,
|
||||
static inline void kvmppc_e500_ref_setup(struct tlbe_ref *ref,
|
||||
struct kvm_book3e_206_tlb_entry *gtlbe,
|
||||
kvm_pfn_t pfn, unsigned int wimg)
|
||||
kvm_pfn_t pfn, unsigned int wimg,
|
||||
bool writable)
|
||||
{
|
||||
ref->pfn = pfn;
|
||||
ref->flags = E500_TLB_VALID;
|
||||
if (writable)
|
||||
ref->flags |= E500_TLB_WRITABLE;
|
||||
|
||||
/* Use guest supplied MAS2_G and MAS2_E */
|
||||
ref->flags |= (gtlbe->mas2 & MAS2_ATTRIB_MASK) | wimg;
|
||||
|
||||
return tlbe_is_writable(gtlbe);
|
||||
}
|
||||
|
||||
static inline void kvmppc_e500_ref_release(struct tlbe_ref *ref)
|
||||
|
|
@ -305,6 +309,7 @@ static void kvmppc_e500_setup_stlbe(
|
|||
{
|
||||
kvm_pfn_t pfn = ref->pfn;
|
||||
u32 pr = vcpu->arch.shared->msr & MSR_PR;
|
||||
bool writable = !!(ref->flags & E500_TLB_WRITABLE);
|
||||
|
||||
BUG_ON(!(ref->flags & E500_TLB_VALID));
|
||||
|
||||
|
|
@ -312,7 +317,7 @@ static void kvmppc_e500_setup_stlbe(
|
|||
stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID;
|
||||
stlbe->mas2 = (gvaddr & MAS2_EPN) | (ref->flags & E500_TLB_MAS2_ATTR);
|
||||
stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) |
|
||||
e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
|
||||
e500_shadow_mas3_attrib(gtlbe->mas7_3, writable, pr);
|
||||
}
|
||||
|
||||
static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
|
||||
|
|
@ -321,15 +326,14 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
|
|||
struct tlbe_ref *ref)
|
||||
{
|
||||
struct kvm_memory_slot *slot;
|
||||
unsigned long pfn = 0; /* silence GCC warning */
|
||||
unsigned int psize;
|
||||
unsigned long pfn;
|
||||
struct page *page = NULL;
|
||||
unsigned long hva;
|
||||
int pfnmap = 0;
|
||||
int tsize = BOOK3E_PAGESZ_4K;
|
||||
int ret = 0;
|
||||
unsigned long mmu_seq;
|
||||
struct kvm *kvm = vcpu_e500->vcpu.kvm;
|
||||
unsigned long tsize_pages = 0;
|
||||
pte_t *ptep;
|
||||
unsigned int wimg = 0;
|
||||
pgd_t *pgdir;
|
||||
|
|
@ -351,110 +355,12 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
|
|||
slot = gfn_to_memslot(vcpu_e500->vcpu.kvm, gfn);
|
||||
hva = gfn_to_hva_memslot(slot, gfn);
|
||||
|
||||
if (tlbsel == 1) {
|
||||
struct vm_area_struct *vma;
|
||||
mmap_read_lock(kvm->mm);
|
||||
|
||||
vma = find_vma(kvm->mm, hva);
|
||||
if (vma && hva >= vma->vm_start &&
|
||||
(vma->vm_flags & VM_PFNMAP)) {
|
||||
/*
|
||||
* This VMA is a physically contiguous region (e.g.
|
||||
* /dev/mem) that bypasses normal Linux page
|
||||
* management. Find the overlap between the
|
||||
* vma and the memslot.
|
||||
*/
|
||||
|
||||
unsigned long start, end;
|
||||
unsigned long slot_start, slot_end;
|
||||
|
||||
pfnmap = 1;
|
||||
|
||||
start = vma->vm_pgoff;
|
||||
end = start +
|
||||
vma_pages(vma);
|
||||
|
||||
pfn = start + ((hva - vma->vm_start) >> PAGE_SHIFT);
|
||||
|
||||
slot_start = pfn - (gfn - slot->base_gfn);
|
||||
slot_end = slot_start + slot->npages;
|
||||
|
||||
if (start < slot_start)
|
||||
start = slot_start;
|
||||
if (end > slot_end)
|
||||
end = slot_end;
|
||||
|
||||
tsize = (gtlbe->mas1 & MAS1_TSIZE_MASK) >>
|
||||
MAS1_TSIZE_SHIFT;
|
||||
|
||||
/*
|
||||
* e500 doesn't implement the lowest tsize bit,
|
||||
* or 1K pages.
|
||||
*/
|
||||
tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
|
||||
|
||||
/*
|
||||
* Now find the largest tsize (up to what the guest
|
||||
* requested) that will cover gfn, stay within the
|
||||
* range, and for which gfn and pfn are mutually
|
||||
* aligned.
|
||||
*/
|
||||
|
||||
for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) {
|
||||
unsigned long gfn_start, gfn_end;
|
||||
tsize_pages = 1UL << (tsize - 2);
|
||||
|
||||
gfn_start = gfn & ~(tsize_pages - 1);
|
||||
gfn_end = gfn_start + tsize_pages;
|
||||
|
||||
if (gfn_start + pfn - gfn < start)
|
||||
continue;
|
||||
if (gfn_end + pfn - gfn > end)
|
||||
continue;
|
||||
if ((gfn & (tsize_pages - 1)) !=
|
||||
(pfn & (tsize_pages - 1)))
|
||||
continue;
|
||||
|
||||
gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1);
|
||||
pfn &= ~(tsize_pages - 1);
|
||||
break;
|
||||
}
|
||||
} else if (vma && hva >= vma->vm_start &&
|
||||
is_vm_hugetlb_page(vma)) {
|
||||
unsigned long psize = vma_kernel_pagesize(vma);
|
||||
|
||||
tsize = (gtlbe->mas1 & MAS1_TSIZE_MASK) >>
|
||||
MAS1_TSIZE_SHIFT;
|
||||
|
||||
/*
|
||||
* Take the largest page size that satisfies both host
|
||||
* and guest mapping
|
||||
*/
|
||||
tsize = min(__ilog2(psize) - 10, tsize);
|
||||
|
||||
/*
|
||||
* e500 doesn't implement the lowest tsize bit,
|
||||
* or 1K pages.
|
||||
*/
|
||||
tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
|
||||
}
|
||||
|
||||
mmap_read_unlock(kvm->mm);
|
||||
}
|
||||
|
||||
if (likely(!pfnmap)) {
|
||||
tsize_pages = 1UL << (tsize + 10 - PAGE_SHIFT);
|
||||
pfn = __kvm_faultin_pfn(slot, gfn, FOLL_WRITE, NULL, &page);
|
||||
if (is_error_noslot_pfn(pfn)) {
|
||||
if (printk_ratelimit())
|
||||
pr_err("%s: real page not found for gfn %lx\n",
|
||||
__func__, (long)gfn);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Align guest and physical address to page map boundaries */
|
||||
pfn &= ~(tsize_pages - 1);
|
||||
gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1);
|
||||
pfn = __kvm_faultin_pfn(slot, gfn, FOLL_WRITE, &writable, &page);
|
||||
if (is_error_noslot_pfn(pfn)) {
|
||||
if (printk_ratelimit())
|
||||
pr_err("%s: real page not found for gfn %lx\n",
|
||||
__func__, (long)gfn);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock(&kvm->mmu_lock);
|
||||
|
|
@ -472,14 +378,13 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
|
|||
* can't run hence pfn won't change.
|
||||
*/
|
||||
local_irq_save(flags);
|
||||
ptep = find_linux_pte(pgdir, hva, NULL, NULL);
|
||||
ptep = find_linux_pte(pgdir, hva, NULL, &psize);
|
||||
if (ptep) {
|
||||
pte_t pte = READ_ONCE(*ptep);
|
||||
|
||||
if (pte_present(pte)) {
|
||||
wimg = (pte_val(pte) >> PTE_WIMGE_SHIFT) &
|
||||
MAS2_WIMGE_MASK;
|
||||
local_irq_restore(flags);
|
||||
} else {
|
||||
local_irq_restore(flags);
|
||||
pr_err_ratelimited("%s: pte not present: gfn %lx,pfn %lx\n",
|
||||
|
|
@ -488,10 +393,72 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
|
|||
goto out;
|
||||
}
|
||||
}
|
||||
writable = kvmppc_e500_ref_setup(ref, gtlbe, pfn, wimg);
|
||||
local_irq_restore(flags);
|
||||
|
||||
if (psize && tlbsel == 1) {
|
||||
unsigned long psize_pages, tsize_pages;
|
||||
unsigned long start, end;
|
||||
unsigned long slot_start, slot_end;
|
||||
|
||||
psize_pages = 1UL << (psize - PAGE_SHIFT);
|
||||
start = pfn & ~(psize_pages - 1);
|
||||
end = start + psize_pages;
|
||||
|
||||
slot_start = pfn - (gfn - slot->base_gfn);
|
||||
slot_end = slot_start + slot->npages;
|
||||
|
||||
if (start < slot_start)
|
||||
start = slot_start;
|
||||
if (end > slot_end)
|
||||
end = slot_end;
|
||||
|
||||
tsize = (gtlbe->mas1 & MAS1_TSIZE_MASK) >>
|
||||
MAS1_TSIZE_SHIFT;
|
||||
|
||||
/*
|
||||
* Any page size that doesn't satisfy the host mapping
|
||||
* will fail the start and end tests.
|
||||
*/
|
||||
tsize = min(psize - PAGE_SHIFT + BOOK3E_PAGESZ_4K, tsize);
|
||||
|
||||
/*
|
||||
* e500 doesn't implement the lowest tsize bit,
|
||||
* or 1K pages.
|
||||
*/
|
||||
tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
|
||||
|
||||
/*
|
||||
* Now find the largest tsize (up to what the guest
|
||||
* requested) that will cover gfn, stay within the
|
||||
* range, and for which gfn and pfn are mutually
|
||||
* aligned.
|
||||
*/
|
||||
|
||||
for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) {
|
||||
unsigned long gfn_start, gfn_end;
|
||||
tsize_pages = 1UL << (tsize - 2);
|
||||
|
||||
gfn_start = gfn & ~(tsize_pages - 1);
|
||||
gfn_end = gfn_start + tsize_pages;
|
||||
|
||||
if (gfn_start + pfn - gfn < start)
|
||||
continue;
|
||||
if (gfn_end + pfn - gfn > end)
|
||||
continue;
|
||||
if ((gfn & (tsize_pages - 1)) !=
|
||||
(pfn & (tsize_pages - 1)))
|
||||
continue;
|
||||
|
||||
gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1);
|
||||
pfn &= ~(tsize_pages - 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
kvmppc_e500_ref_setup(ref, gtlbe, pfn, wimg, writable);
|
||||
kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize,
|
||||
ref, gvaddr, stlbe);
|
||||
writable = tlbe_is_writable(stlbe);
|
||||
|
||||
/* Clear i-cache for new pages */
|
||||
kvmppc_mmu_flush_icache(pfn);
|
||||
|
|
|
|||
|
|
@ -2678,9 +2678,13 @@ static int flic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
|
|||
kvm_s390_clear_float_irqs(dev->kvm);
|
||||
break;
|
||||
case KVM_DEV_FLIC_APF_ENABLE:
|
||||
if (kvm_is_ucontrol(dev->kvm))
|
||||
return -EINVAL;
|
||||
dev->kvm->arch.gmap->pfault_enabled = 1;
|
||||
break;
|
||||
case KVM_DEV_FLIC_APF_DISABLE_WAIT:
|
||||
if (kvm_is_ucontrol(dev->kvm))
|
||||
return -EINVAL;
|
||||
dev->kvm->arch.gmap->pfault_enabled = 0;
|
||||
/*
|
||||
* Make sure no async faults are in transition when
|
||||
|
|
@ -2894,6 +2898,8 @@ int kvm_set_routing_entry(struct kvm *kvm,
|
|||
switch (ue->type) {
|
||||
/* we store the userspace addresses instead of the guest addresses */
|
||||
case KVM_IRQ_ROUTING_S390_ADAPTER:
|
||||
if (kvm_is_ucontrol(kvm))
|
||||
return -EINVAL;
|
||||
e->set = set_adapter_int;
|
||||
uaddr = gmap_translate(kvm->arch.gmap, ue->u.adapter.summary_addr);
|
||||
if (uaddr == -EFAULT)
|
||||
|
|
|
|||
|
|
@ -854,7 +854,7 @@ unpin:
|
|||
static void unpin_scb(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page,
|
||||
gpa_t gpa)
|
||||
{
|
||||
hpa_t hpa = (hpa_t) vsie_page->scb_o;
|
||||
hpa_t hpa = virt_to_phys(vsie_page->scb_o);
|
||||
|
||||
if (hpa)
|
||||
unpin_guest_page(vcpu->kvm, gpa, hpa);
|
||||
|
|
|
|||
|
|
@ -53,8 +53,7 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1);
|
|||
void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
|
||||
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
|
||||
void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
|
||||
void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
|
||||
void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
|
||||
void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val);
|
||||
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
|
||||
void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
|
||||
bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
|
||||
|
|
@ -127,8 +126,7 @@ static inline u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu)
|
|||
static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
|
||||
static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
|
||||
static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
|
||||
static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
|
||||
static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
|
||||
static inline void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
|
||||
static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
|
||||
static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
|
||||
static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
|
||||
|
|
|
|||
|
|
@ -152,7 +152,6 @@ static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
|
|||
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
|
||||
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
|
||||
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
|
||||
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0),
|
||||
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
|
||||
REG_FTR_END,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -210,10 +210,13 @@ TEST_F(uc_kvm, uc_attr_mem_limit)
|
|||
struct kvm_device_attr attr = {
|
||||
.group = KVM_S390_VM_MEM_CTRL,
|
||||
.attr = KVM_S390_VM_MEM_LIMIT_SIZE,
|
||||
.addr = (unsigned long)&limit,
|
||||
.addr = (u64)&limit,
|
||||
};
|
||||
int rc;
|
||||
|
||||
rc = ioctl(self->vm_fd, KVM_HAS_DEVICE_ATTR, &attr);
|
||||
EXPECT_EQ(0, rc);
|
||||
|
||||
rc = ioctl(self->vm_fd, KVM_GET_DEVICE_ATTR, &attr);
|
||||
EXPECT_EQ(0, rc);
|
||||
EXPECT_EQ(~0UL, limit);
|
||||
|
|
@ -635,4 +638,171 @@ TEST_F(uc_kvm, uc_skey)
|
|||
uc_assert_diag44(self);
|
||||
}
|
||||
|
||||
static char uc_flic_b[PAGE_SIZE];
|
||||
static struct kvm_s390_io_adapter uc_flic_ioa = { .id = 0 };
|
||||
static struct kvm_s390_io_adapter_req uc_flic_ioam = { .id = 0 };
|
||||
static struct kvm_s390_ais_req uc_flic_asim = { .isc = 0 };
|
||||
static struct kvm_s390_ais_all uc_flic_asima = { .simm = 0 };
|
||||
static struct uc_flic_attr_test {
|
||||
char *name;
|
||||
struct kvm_device_attr a;
|
||||
int hasrc;
|
||||
int geterrno;
|
||||
int seterrno;
|
||||
} uc_flic_attr_tests[] = {
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_GET_ALL_IRQS",
|
||||
.seterrno = EINVAL,
|
||||
.a = {
|
||||
.group = KVM_DEV_FLIC_GET_ALL_IRQS,
|
||||
.addr = (u64)&uc_flic_b,
|
||||
.attr = PAGE_SIZE,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_ENQUEUE",
|
||||
.geterrno = EINVAL,
|
||||
.a = { .group = KVM_DEV_FLIC_ENQUEUE, },
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_CLEAR_IRQS",
|
||||
.geterrno = EINVAL,
|
||||
.a = { .group = KVM_DEV_FLIC_CLEAR_IRQS, },
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_ADAPTER_REGISTER",
|
||||
.geterrno = EINVAL,
|
||||
.a = {
|
||||
.group = KVM_DEV_FLIC_ADAPTER_REGISTER,
|
||||
.addr = (u64)&uc_flic_ioa,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_ADAPTER_MODIFY",
|
||||
.geterrno = EINVAL,
|
||||
.seterrno = EINVAL,
|
||||
.a = {
|
||||
.group = KVM_DEV_FLIC_ADAPTER_MODIFY,
|
||||
.addr = (u64)&uc_flic_ioam,
|
||||
.attr = sizeof(uc_flic_ioam),
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_CLEAR_IO_IRQ",
|
||||
.geterrno = EINVAL,
|
||||
.seterrno = EINVAL,
|
||||
.a = {
|
||||
.group = KVM_DEV_FLIC_CLEAR_IO_IRQ,
|
||||
.attr = 32,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_AISM",
|
||||
.geterrno = EINVAL,
|
||||
.seterrno = ENOTSUP,
|
||||
.a = {
|
||||
.group = KVM_DEV_FLIC_AISM,
|
||||
.addr = (u64)&uc_flic_asim,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_AIRQ_INJECT",
|
||||
.geterrno = EINVAL,
|
||||
.a = { .group = KVM_DEV_FLIC_AIRQ_INJECT, },
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_AISM_ALL",
|
||||
.geterrno = ENOTSUP,
|
||||
.seterrno = ENOTSUP,
|
||||
.a = {
|
||||
.group = KVM_DEV_FLIC_AISM_ALL,
|
||||
.addr = (u64)&uc_flic_asima,
|
||||
.attr = sizeof(uc_flic_asima),
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_APF_ENABLE",
|
||||
.geterrno = EINVAL,
|
||||
.seterrno = EINVAL,
|
||||
.a = { .group = KVM_DEV_FLIC_APF_ENABLE, },
|
||||
},
|
||||
{
|
||||
.name = "KVM_DEV_FLIC_APF_DISABLE_WAIT",
|
||||
.geterrno = EINVAL,
|
||||
.seterrno = EINVAL,
|
||||
.a = { .group = KVM_DEV_FLIC_APF_DISABLE_WAIT, },
|
||||
},
|
||||
};
|
||||
|
||||
TEST_F(uc_kvm, uc_flic_attrs)
|
||||
{
|
||||
struct kvm_create_device cd = { .type = KVM_DEV_TYPE_FLIC };
|
||||
struct kvm_device_attr attr;
|
||||
u64 value;
|
||||
int rc, i;
|
||||
|
||||
rc = ioctl(self->vm_fd, KVM_CREATE_DEVICE, &cd);
|
||||
ASSERT_EQ(0, rc) TH_LOG("create device failed with err %s (%i)",
|
||||
strerror(errno), errno);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uc_flic_attr_tests); i++) {
|
||||
TH_LOG("test %s", uc_flic_attr_tests[i].name);
|
||||
attr = (struct kvm_device_attr) {
|
||||
.group = uc_flic_attr_tests[i].a.group,
|
||||
.attr = uc_flic_attr_tests[i].a.attr,
|
||||
.addr = uc_flic_attr_tests[i].a.addr,
|
||||
};
|
||||
if (attr.addr == 0)
|
||||
attr.addr = (u64)&value;
|
||||
|
||||
rc = ioctl(cd.fd, KVM_HAS_DEVICE_ATTR, &attr);
|
||||
EXPECT_EQ(uc_flic_attr_tests[i].hasrc, !!rc)
|
||||
TH_LOG("expected dev attr missing %s",
|
||||
uc_flic_attr_tests[i].name);
|
||||
|
||||
rc = ioctl(cd.fd, KVM_GET_DEVICE_ATTR, &attr);
|
||||
EXPECT_EQ(!!uc_flic_attr_tests[i].geterrno, !!rc)
|
||||
TH_LOG("get dev attr rc not expected on %s %s (%i)",
|
||||
uc_flic_attr_tests[i].name,
|
||||
strerror(errno), errno);
|
||||
if (uc_flic_attr_tests[i].geterrno)
|
||||
EXPECT_EQ(uc_flic_attr_tests[i].geterrno, errno)
|
||||
TH_LOG("get dev attr errno not expected on %s %s (%i)",
|
||||
uc_flic_attr_tests[i].name,
|
||||
strerror(errno), errno);
|
||||
|
||||
rc = ioctl(cd.fd, KVM_SET_DEVICE_ATTR, &attr);
|
||||
EXPECT_EQ(!!uc_flic_attr_tests[i].seterrno, !!rc)
|
||||
TH_LOG("set sev attr rc not expected on %s %s (%i)",
|
||||
uc_flic_attr_tests[i].name,
|
||||
strerror(errno), errno);
|
||||
if (uc_flic_attr_tests[i].seterrno)
|
||||
EXPECT_EQ(uc_flic_attr_tests[i].seterrno, errno)
|
||||
TH_LOG("set dev attr errno not expected on %s %s (%i)",
|
||||
uc_flic_attr_tests[i].name,
|
||||
strerror(errno), errno);
|
||||
}
|
||||
|
||||
close(cd.fd);
|
||||
}
|
||||
|
||||
TEST_F(uc_kvm, uc_set_gsi_routing)
|
||||
{
|
||||
struct kvm_irq_routing *routing = kvm_gsi_routing_create();
|
||||
struct kvm_irq_routing_entry ue = {
|
||||
.type = KVM_IRQ_ROUTING_S390_ADAPTER,
|
||||
.gsi = 1,
|
||||
.u.adapter = (struct kvm_irq_routing_s390_adapter) {
|
||||
.ind_addr = 0,
|
||||
},
|
||||
};
|
||||
int rc;
|
||||
|
||||
routing->entries[0] = ue;
|
||||
routing->nr = 1;
|
||||
rc = ioctl(self->vm_fd, KVM_SET_GSI_ROUTING, routing);
|
||||
ASSERT_EQ(-1, rc) TH_LOG("err %s (%i)", strerror(errno), errno);
|
||||
ASSERT_EQ(EINVAL, errno) TH_LOG("err %s (%i)", strerror(errno), errno);
|
||||
}
|
||||
|
||||
TEST_HARNESS_MAIN
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue