drm/amd/swsmu: add aldebaran smu13 ip support (v3)
Add initial swSMU support. v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth) v2: switch to thm/mp v13_0 ip headers (Hawking) v3: squash in updates (Alex) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kevin Wang
Alex Deucher
parent
465c437aac
commit
c05d1c4015
12 changed files with 3797 additions and 5 deletions
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@ -27,6 +27,7 @@ subdir-ccflags-y += \
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-I$(FULL_AMD_PATH)/pm/swsmu \
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-I$(FULL_AMD_PATH)/pm/swsmu \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu11 \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu11 \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu12 \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu12 \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu13 \
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-I$(FULL_AMD_PATH)/pm/powerplay \
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-I$(FULL_AMD_PATH)/pm/powerplay \
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-I$(FULL_AMD_PATH)/pm/powerplay/smumgr\
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-I$(FULL_AMD_PATH)/pm/powerplay/smumgr\
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-I$(FULL_AMD_PATH)/pm/powerplay/hwmgr
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-I$(FULL_AMD_PATH)/pm/powerplay/hwmgr
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109
drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h
Normal file
109
drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h
Normal file
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@ -0,0 +1,109 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef ALDEBARAN_PP_SMC_H
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#define ALDEBARAN_PP_SMC_H
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#pragma pack(push, 1)
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// SMU Response Codes:
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#define PPSMC_Result_OK 0x1
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#define PPSMC_Result_Failed 0xFF
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#define PPSMC_Result_UnknownCmd 0xFE
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#define PPSMC_Result_CmdRejectedPrereq 0xFD
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#define PPSMC_Result_CmdRejectedBusy 0xFC
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// Message Definitions:
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#define PPSMC_MSG_TestMessage 0x1
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#define PPSMC_MSG_GetSmuVersion 0x2
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#define PPSMC_MSG_Mode1Reset 0x3
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#define PPSMC_MSG_GetDriverIfVersion 0x4
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#define PPSMC_MSG_spare1 0x5
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#define PPSMC_MSG_spare2 0x6
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#define PPSMC_MSG_EnableAllSmuFeatures 0x7
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#define PPSMC_MSG_DisableAllSmuFeatures 0x8
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#define PPSMC_MSG_spare3 0x9
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#define PPSMC_MSG_spare4 0xA
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#define PPSMC_MSG_spare5 0xB
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#define PPSMC_MSG_spare6 0xC
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#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xD
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#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xE
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#define PPSMC_MSG_SetDriverDramAddrHigh 0xF
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#define PPSMC_MSG_SetDriverDramAddrLow 0x10
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#define PPSMC_MSG_SetToolsDramAddrHigh 0x11
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#define PPSMC_MSG_SetToolsDramAddrLow 0x12
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#define PPSMC_MSG_TransferTableSmu2Dram 0x13
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#define PPSMC_MSG_TransferTableDram2Smu 0x14
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#define PPSMC_MSG_UseDefaultPPTable 0x15
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#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x16
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#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x17
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#define PPSMC_MSG_SetSoftMinByFreq 0x18
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#define PPSMC_MSG_SetSoftMaxByFreq 0x19
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#define PPSMC_MSG_SetHardMinByFreq 0x1A
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#define PPSMC_MSG_SetHardMaxByFreq 0x1B
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#define PPSMC_MSG_GetMinDpmFreq 0x1C
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#define PPSMC_MSG_GetMaxDpmFreq 0x1D
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#define PPSMC_MSG_GetDpmFreqByIndex 0x1E
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#define PPSMC_MSG_SetWorkloadMask 0x1F
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#define PPSMC_MSG_GetVoltageByDpm 0x20
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#define PPSMC_MSG_GetVoltageByDpmOverdrive 0x21
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#define PPSMC_MSG_SetPptLimit 0x22
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#define PPSMC_MSG_GetPptLimit 0x23
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#define PPSMC_MSG_PrepareMp1ForUnload 0x24
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#define PPSMC_MSG_PrepareMp1ForReset 0x25
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#define PPSMC_MSG_SoftReset 0x26
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#define PPSMC_MSG_RunDcBtc 0x27
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#define PPSMC_MSG_DramLogSetDramAddrHigh 0x28
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#define PPSMC_MSG_DramLogSetDramAddrLow 0x29
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#define PPSMC_MSG_DramLogSetDramSize 0x2A
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#define PPSMC_MSG_GetDebugData 0x2B
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#define PPSMC_MSG_WaflTest 0x2C
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#define PPSMC_MSG_spare7 0x2D
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#define PPSMC_MSG_SetMemoryChannelEnable 0x2E
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#define PPSMC_MSG_SetNumBadHbmPagesRetired 0x2F
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#define PPSMC_MSG_DFCstateControl 0x32
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#define PPSMC_MSG_GetGmiPwrDnHyst 0x33
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#define PPSMC_MSG_SetGmiPwrDnHyst 0x34
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#define PPSMC_MSG_GmiPwrDnControl 0x35
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#define PPSMC_MSG_EnterGfxoff 0x36
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#define PPSMC_MSG_ExitGfxoff 0x37
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#define PPSMC_MSG_SetExecuteDMATest 0x38
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#define PPSMC_MSG_EnableDeterminism 0x39
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#define PPSMC_MSG_DisableDeterminism 0x3A
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#define PPSMC_MSG_SetUclkDpmMode 0x3B
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#define PPSMC_Message_Count 0x3C
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typedef enum {
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GFXOFF_ERROR_NO_ERROR,
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GFXOFF_ERROR_DISALLOWED,
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GFXOFF_ERROR_GFX_BUSY,
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GFXOFF_ERROR_GFX_OFF,
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GFXOFF_ERROR_GFX_ON,
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} GFXOFF_ERROR_e;
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typedef uint32_t PPSMC_Result;
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typedef uint32_t PPSMC_Msg;
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#pragma pack(pop)
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#endif
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@ -1286,6 +1286,7 @@ extern const struct amd_ip_funcs smu_ip_funcs;
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extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
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extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
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extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
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extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
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extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
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bool is_support_sw_smu(struct amdgpu_device *adev);
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bool is_support_sw_smu(struct amdgpu_device *adev);
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bool is_support_cclk_dpm(struct amdgpu_device *adev);
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bool is_support_cclk_dpm(struct amdgpu_device *adev);
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@ -168,9 +168,16 @@
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__SMU_DUMMY_MAP(PowerGateAtHub), \
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__SMU_DUMMY_MAP(PowerGateAtHub), \
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__SMU_DUMMY_MAP(SetSoftMinJpeg), \
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__SMU_DUMMY_MAP(SetSoftMinJpeg), \
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__SMU_DUMMY_MAP(SetHardMinFclkByFreq), \
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__SMU_DUMMY_MAP(SetHardMinFclkByFreq), \
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__SMU_DUMMY_MAP(DFCstateControl), \
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__SMU_DUMMY_MAP(DFCstateControl), \
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__SMU_DUMMY_MAP(GmiPwrDnControl), \
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__SMU_DUMMY_MAP(GmiPwrDnControl), \
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__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE),\
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__SMU_DUMMY_MAP(spare), \
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__SMU_DUMMY_MAP(SetNumBadHbmPagesRetired), \
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__SMU_DUMMY_MAP(GetGmiPwrDnHyst), \
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__SMU_DUMMY_MAP(SetGmiPwrDnHyst), \
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__SMU_DUMMY_MAP(EnterGfxoff), \
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__SMU_DUMMY_MAP(ExitGfxoff), \
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__SMU_DUMMY_MAP(SetExecuteDMATest), \
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__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \
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__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
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__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
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__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
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__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
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__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \
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__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \
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@ -214,6 +221,9 @@
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__SMU_DUMMY_MAP(SetSlowPPTLimit), \
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__SMU_DUMMY_MAP(SetSlowPPTLimit), \
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__SMU_DUMMY_MAP(GetFastPPTLimit), \
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__SMU_DUMMY_MAP(GetFastPPTLimit), \
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__SMU_DUMMY_MAP(GetSlowPPTLimit), \
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__SMU_DUMMY_MAP(GetSlowPPTLimit), \
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__SMU_DUMMY_MAP(EnableDeterminism), \
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__SMU_DUMMY_MAP(DisableDeterminism), \
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__SMU_DUMMY_MAP(SetUclkDpmMode), \
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#undef __SMU_DUMMY_MAP
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#undef __SMU_DUMMY_MAP
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#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
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#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
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@ -239,6 +249,7 @@ enum smu_clk_type {
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SMU_SCLK,
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SMU_SCLK,
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SMU_MCLK,
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SMU_MCLK,
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SMU_PCIE,
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SMU_PCIE,
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SMU_LCLK,
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SMU_OD_CCLK,
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SMU_OD_CCLK,
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SMU_OD_SCLK,
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SMU_OD_SCLK,
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SMU_OD_MCLK,
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SMU_OD_MCLK,
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@ -255,6 +266,7 @@ enum smu_clk_type {
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__SMU_DUMMY_MAP(DPM_SOCCLK), \
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__SMU_DUMMY_MAP(DPM_SOCCLK), \
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__SMU_DUMMY_MAP(DPM_UVD), \
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__SMU_DUMMY_MAP(DPM_UVD), \
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__SMU_DUMMY_MAP(DPM_VCE), \
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__SMU_DUMMY_MAP(DPM_VCE), \
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__SMU_DUMMY_MAP(DPM_LCLK), \
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__SMU_DUMMY_MAP(ULV), \
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__SMU_DUMMY_MAP(ULV), \
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__SMU_DUMMY_MAP(DPM_MP0CLK), \
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__SMU_DUMMY_MAP(DPM_MP0CLK), \
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__SMU_DUMMY_MAP(DPM_LINK), \
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__SMU_DUMMY_MAP(DPM_LINK), \
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@ -283,6 +295,7 @@ enum smu_clk_type {
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__SMU_DUMMY_MAP(DS_MP1CLK), \
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__SMU_DUMMY_MAP(DS_MP1CLK), \
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__SMU_DUMMY_MAP(DS_MP0CLK), \
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__SMU_DUMMY_MAP(DS_MP0CLK), \
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__SMU_DUMMY_MAP(XGMI), \
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__SMU_DUMMY_MAP(XGMI), \
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__SMU_DUMMY_MAP(XGMI_PER_LINK_PWR_DWN), \
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__SMU_DUMMY_MAP(DPM_GFX_PACE), \
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__SMU_DUMMY_MAP(DPM_GFX_PACE), \
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__SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \
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__SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \
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__SMU_DUMMY_MAP(MEM_MVDD_SCALING), \
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__SMU_DUMMY_MAP(MEM_MVDD_SCALING), \
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@ -304,6 +317,7 @@ enum smu_clk_type {
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__SMU_DUMMY_MAP(MMHUB_PG), \
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__SMU_DUMMY_MAP(MMHUB_PG), \
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__SMU_DUMMY_MAP(ATHUB_PG), \
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__SMU_DUMMY_MAP(ATHUB_PG), \
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__SMU_DUMMY_MAP(APCC_DFLL), \
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__SMU_DUMMY_MAP(APCC_DFLL), \
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__SMU_DUMMY_MAP(DF_CSTATE), \
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__SMU_DUMMY_MAP(DPM_GFX_GPO), \
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__SMU_DUMMY_MAP(DPM_GFX_GPO), \
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__SMU_DUMMY_MAP(WAFL_CG), \
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__SMU_DUMMY_MAP(WAFL_CG), \
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__SMU_DUMMY_MAP(CCLK_DPM), \
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__SMU_DUMMY_MAP(CCLK_DPM), \
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@ -335,7 +349,12 @@ enum smu_clk_type {
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__SMU_DUMMY_MAP(ISP_DPM), \
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__SMU_DUMMY_MAP(ISP_DPM), \
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__SMU_DUMMY_MAP(A55_DPM), \
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__SMU_DUMMY_MAP(A55_DPM), \
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__SMU_DUMMY_MAP(CVIP_DSP_DPM), \
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__SMU_DUMMY_MAP(CVIP_DSP_DPM), \
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__SMU_DUMMY_MAP(MSMU_LOW_POWER),
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__SMU_DUMMY_MAP(MSMU_LOW_POWER), \
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__SMU_DUMMY_MAP(FUSE_CG), \
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__SMU_DUMMY_MAP(MP1_CG), \
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__SMU_DUMMY_MAP(SMUIO_CG), \
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__SMU_DUMMY_MAP(THM_CG), \
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__SMU_DUMMY_MAP(CLK_CG), \
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#undef __SMU_DUMMY_MAP
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#undef __SMU_DUMMY_MAP
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#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT
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#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT
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273
drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
Normal file
273
drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
Normal file
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@ -0,0 +1,273 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SMU_V13_0_H__
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#define __SMU_V13_0_H__
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#include "amdgpu_smu.h"
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#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
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#define SMU13_DRIVER_IF_VERSION_ALDE 0x5
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/* MP Apertures */
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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#define smnMP0_FW_INTF 0x30101c0
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#define smnMP1_PUB_CTRL 0x3010b14
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#define TEMP_RANGE_MIN (0)
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#define TEMP_RANGE_MAX (80 * 1000)
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#define SMU13_TOOL_SIZE 0x19000
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#define MAX_DPM_LEVELS 16
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#define MAX_PCIE_CONF 2
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#define CTF_OFFSET_EDGE 5
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#define CTF_OFFSET_HOTSPOT 5
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#define CTF_OFFSET_MEM 5
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static const struct smu_temperature_range smu13_thermal_policy[] =
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{
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|
{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
|
||||||
|
{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_13_0_max_sustainable_clocks {
|
||||||
|
uint32_t display_clock;
|
||||||
|
uint32_t phy_clock;
|
||||||
|
uint32_t pixel_clock;
|
||||||
|
uint32_t uclock;
|
||||||
|
uint32_t dcef_clock;
|
||||||
|
uint32_t soc_clock;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_13_0_dpm_clk_level {
|
||||||
|
bool enabled;
|
||||||
|
uint32_t value;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_13_0_dpm_table {
|
||||||
|
uint32_t min; /* MHz */
|
||||||
|
uint32_t max; /* MHz */
|
||||||
|
uint32_t count;
|
||||||
|
struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_13_0_pcie_table {
|
||||||
|
uint8_t pcie_gen[MAX_PCIE_CONF];
|
||||||
|
uint8_t pcie_lane[MAX_PCIE_CONF];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_13_0_dpm_tables {
|
||||||
|
struct smu_13_0_dpm_table soc_table;
|
||||||
|
struct smu_13_0_dpm_table gfx_table;
|
||||||
|
struct smu_13_0_dpm_table uclk_table;
|
||||||
|
struct smu_13_0_dpm_table eclk_table;
|
||||||
|
struct smu_13_0_dpm_table vclk_table;
|
||||||
|
struct smu_13_0_dpm_table dclk_table;
|
||||||
|
struct smu_13_0_dpm_table dcef_table;
|
||||||
|
struct smu_13_0_dpm_table pixel_table;
|
||||||
|
struct smu_13_0_dpm_table display_table;
|
||||||
|
struct smu_13_0_dpm_table phy_table;
|
||||||
|
struct smu_13_0_dpm_table fclk_table;
|
||||||
|
struct smu_13_0_pcie_table pcie_table;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_13_0_dpm_context {
|
||||||
|
struct smu_13_0_dpm_tables dpm_tables;
|
||||||
|
uint32_t workload_policy_mask;
|
||||||
|
uint32_t dcef_min_ds_clk;
|
||||||
|
};
|
||||||
|
|
||||||
|
enum smu_13_0_power_state {
|
||||||
|
SMU_13_0_POWER_STATE__D0 = 0,
|
||||||
|
SMU_13_0_POWER_STATE__D1,
|
||||||
|
SMU_13_0_POWER_STATE__D3, /* Sleep*/
|
||||||
|
SMU_13_0_POWER_STATE__D4, /* Hibernate*/
|
||||||
|
SMU_13_0_POWER_STATE__D5, /* Power off*/
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_13_0_power_context {
|
||||||
|
uint32_t power_source;
|
||||||
|
uint8_t in_power_limit_boost_mode;
|
||||||
|
enum smu_13_0_power_state power_state;
|
||||||
|
};
|
||||||
|
|
||||||
|
enum smu_v13_0_baco_seq {
|
||||||
|
BACO_SEQ_BACO = 0,
|
||||||
|
BACO_SEQ_MSR,
|
||||||
|
BACO_SEQ_BAMACO,
|
||||||
|
BACO_SEQ_ULPS,
|
||||||
|
BACO_SEQ_COUNT,
|
||||||
|
};
|
||||||
|
|
||||||
|
#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
|
||||||
|
|
||||||
|
int smu_v13_0_init_microcode(struct smu_context *smu);
|
||||||
|
|
||||||
|
void smu_v13_0_fini_microcode(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_load_microcode(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_init_smc_tables(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_fini_smc_tables(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_init_power(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_fini_power(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_check_fw_status(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_setup_pptable(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_check_fw_version(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_set_driver_table_location(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_set_tool_table_location(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_system_features_control(struct smu_context *smu,
|
||||||
|
bool en);
|
||||||
|
|
||||||
|
int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
|
||||||
|
|
||||||
|
int smu_v13_0_set_allowed_mask(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_notify_display_change(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_current_power_limit(struct smu_context *smu,
|
||||||
|
uint32_t *power_limit);
|
||||||
|
|
||||||
|
int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n);
|
||||||
|
|
||||||
|
int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
|
||||||
|
|
||||||
|
int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
|
||||||
|
|
||||||
|
int
|
||||||
|
smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
|
||||||
|
struct pp_display_clock_request
|
||||||
|
*clock_req);
|
||||||
|
|
||||||
|
uint32_t
|
||||||
|
smu_v13_0_get_fan_control_mode(struct smu_context *smu);
|
||||||
|
|
||||||
|
int
|
||||||
|
smu_v13_0_set_fan_control_mode(struct smu_context *smu,
|
||||||
|
uint32_t mode);
|
||||||
|
|
||||||
|
int
|
||||||
|
smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
|
||||||
|
|
||||||
|
int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
|
||||||
|
uint32_t speed);
|
||||||
|
|
||||||
|
int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
|
||||||
|
uint32_t pstate);
|
||||||
|
|
||||||
|
int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
|
||||||
|
|
||||||
|
int smu_v13_0_register_irq_handler(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
|
||||||
|
struct pp_smu_nv_clock_table *max_clocks);
|
||||||
|
|
||||||
|
bool smu_v13_0_baco_is_support(struct smu_context *smu);
|
||||||
|
|
||||||
|
enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
|
||||||
|
|
||||||
|
int smu_v13_0_baco_enter(struct smu_context *smu);
|
||||||
|
int smu_v13_0_baco_exit(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_mode1_reset(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
|
||||||
|
uint32_t *min, uint32_t *max);
|
||||||
|
|
||||||
|
int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
|
||||||
|
uint32_t min, uint32_t max);
|
||||||
|
|
||||||
|
int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
|
||||||
|
enum smu_clk_type clk_type,
|
||||||
|
uint32_t min,
|
||||||
|
uint32_t max);
|
||||||
|
|
||||||
|
int smu_v13_0_set_performance_level(struct smu_context *smu,
|
||||||
|
enum amd_dpm_forced_level level);
|
||||||
|
|
||||||
|
int smu_v13_0_set_power_source(struct smu_context *smu,
|
||||||
|
enum smu_power_src_type power_src);
|
||||||
|
|
||||||
|
int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
|
||||||
|
enum smu_clk_type clk_type,
|
||||||
|
uint16_t level,
|
||||||
|
uint32_t *value);
|
||||||
|
|
||||||
|
int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
|
||||||
|
enum smu_clk_type clk_type,
|
||||||
|
uint32_t *value);
|
||||||
|
|
||||||
|
int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
|
||||||
|
enum smu_clk_type clk_type,
|
||||||
|
struct smu_13_0_dpm_table *single_dpm_table);
|
||||||
|
|
||||||
|
int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
|
||||||
|
enum smu_clk_type clk_type,
|
||||||
|
uint32_t *min_value,
|
||||||
|
uint32_t *max_value);
|
||||||
|
|
||||||
|
int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
|
||||||
|
|
||||||
|
int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
|
||||||
|
|
||||||
|
void smu_v13_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
|
||||||
|
|
||||||
|
int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
|
||||||
|
bool enablement);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
165
drivers/gpu/drm/amd/pm/inc/smu_v13_0_pptable.h
Normal file
165
drivers/gpu/drm/amd/pm/inc/smu_v13_0_pptable.h
Normal file
|
|
@ -0,0 +1,165 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
#ifndef SMU_13_0_PPTABLE_H
|
||||||
|
#define SMU_13_0_PPTABLE_H
|
||||||
|
|
||||||
|
#define SMU_13_0_TABLE_FORMAT_REVISION 1
|
||||||
|
|
||||||
|
//// POWERPLAYTABLE::ulPlatformCaps
|
||||||
|
#define SMU_13_0_PP_PLATFORM_CAP_POWERPLAY 0x1
|
||||||
|
#define SMU_13_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2
|
||||||
|
#define SMU_13_0_PP_PLATFORM_CAP_HARDWAREDC 0x4
|
||||||
|
#define SMU_13_0_PP_PLATFORM_CAP_BACO 0x8
|
||||||
|
#define SMU_13_0_PP_PLATFORM_CAP_MACO 0x10
|
||||||
|
#define SMU_13_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20
|
||||||
|
|
||||||
|
// SMU_13_0_PP_THERMALCONTROLLER - Thermal Controller Type
|
||||||
|
#define SMU_13_0_PP_THERMALCONTROLLER_NONE 0
|
||||||
|
|
||||||
|
#define SMU_13_0_PP_OVERDRIVE_VERSION 0x0800
|
||||||
|
#define SMU_13_0_PP_POWERSAVINGCLOCK_VERSION 0x0100
|
||||||
|
|
||||||
|
enum SMU_13_0_ODFEATURE_CAP {
|
||||||
|
SMU_13_0_ODCAP_GFXCLK_LIMITS = 0,
|
||||||
|
SMU_13_0_ODCAP_GFXCLK_CURVE,
|
||||||
|
SMU_13_0_ODCAP_UCLK_MAX,
|
||||||
|
SMU_13_0_ODCAP_POWER_LIMIT,
|
||||||
|
SMU_13_0_ODCAP_FAN_ACOUSTIC_LIMIT,
|
||||||
|
SMU_13_0_ODCAP_FAN_SPEED_MIN,
|
||||||
|
SMU_13_0_ODCAP_TEMPERATURE_FAN,
|
||||||
|
SMU_13_0_ODCAP_TEMPERATURE_SYSTEM,
|
||||||
|
SMU_13_0_ODCAP_MEMORY_TIMING_TUNE,
|
||||||
|
SMU_13_0_ODCAP_FAN_ZERO_RPM_CONTROL,
|
||||||
|
SMU_13_0_ODCAP_AUTO_UV_ENGINE,
|
||||||
|
SMU_13_0_ODCAP_AUTO_OC_ENGINE,
|
||||||
|
SMU_13_0_ODCAP_AUTO_OC_MEMORY,
|
||||||
|
SMU_13_0_ODCAP_FAN_CURVE,
|
||||||
|
SMU_13_0_ODCAP_COUNT,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum SMU_13_0_ODFEATURE_ID {
|
||||||
|
SMU_13_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_13_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
|
||||||
|
SMU_13_0_ODFEATURE_GFXCLK_CURVE = 1 << SMU_13_0_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature
|
||||||
|
SMU_13_0_ODFEATURE_UCLK_MAX = 1 << SMU_13_0_ODCAP_UCLK_MAX, //UCLK Limit feature
|
||||||
|
SMU_13_0_ODFEATURE_POWER_LIMIT = 1 << SMU_13_0_ODCAP_POWER_LIMIT, //Power Limit feature
|
||||||
|
SMU_13_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature
|
||||||
|
SMU_13_0_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_13_0_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature
|
||||||
|
SMU_13_0_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_13_0_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature
|
||||||
|
SMU_13_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_13_0_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature
|
||||||
|
SMU_13_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_13_0_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature
|
||||||
|
SMU_13_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_13_0_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature
|
||||||
|
SMU_13_0_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_13_0_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature
|
||||||
|
SMU_13_0_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_13_0_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature
|
||||||
|
SMU_13_0_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_13_0_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature
|
||||||
|
SMU_13_0_ODFEATURE_FAN_CURVE = 1 << SMU_13_0_ODCAP_FAN_CURVE, //Fan Curve feature
|
||||||
|
SMU_13_0_ODFEATURE_COUNT = 14,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SMU_13_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
|
||||||
|
|
||||||
|
enum SMU_13_0_ODSETTING_ID {
|
||||||
|
SMU_13_0_ODSETTING_GFXCLKFMAX = 0,
|
||||||
|
SMU_13_0_ODSETTING_GFXCLKFMIN,
|
||||||
|
SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P1,
|
||||||
|
SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
|
||||||
|
SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P2,
|
||||||
|
SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
|
||||||
|
SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P3,
|
||||||
|
SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
|
||||||
|
SMU_13_0_ODSETTING_UCLKFMAX,
|
||||||
|
SMU_13_0_ODSETTING_POWERPERCENTAGE,
|
||||||
|
SMU_13_0_ODSETTING_FANRPMMIN,
|
||||||
|
SMU_13_0_ODSETTING_FANRPMACOUSTICLIMIT,
|
||||||
|
SMU_13_0_ODSETTING_FANTARGETTEMPERATURE,
|
||||||
|
SMU_13_0_ODSETTING_OPERATINGTEMPMAX,
|
||||||
|
SMU_13_0_ODSETTING_ACTIMING,
|
||||||
|
SMU_13_0_ODSETTING_FAN_ZERO_RPM_CONTROL,
|
||||||
|
SMU_13_0_ODSETTING_AUTOUVENGINE,
|
||||||
|
SMU_13_0_ODSETTING_AUTOOCENGINE,
|
||||||
|
SMU_13_0_ODSETTING_AUTOOCMEMORY,
|
||||||
|
SMU_13_0_ODSETTING_COUNT,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SMU_13_0_MAX_ODSETTING 32 //Maximum Number of ODSettings
|
||||||
|
|
||||||
|
struct smu_13_0_overdrive_table {
|
||||||
|
uint8_t revision; //Revision = SMU_11_0_PP_OVERDRIVE_VERSION
|
||||||
|
uint8_t reserve[3]; //Zero filled field reserved for future use
|
||||||
|
uint32_t feature_count; //Total number of supported features
|
||||||
|
uint32_t setting_count; //Total number of supported settings
|
||||||
|
uint8_t cap[SMU_13_0_MAX_ODFEATURE]; //OD feature support flags
|
||||||
|
uint32_t max[SMU_13_0_MAX_ODSETTING]; //default maximum settings
|
||||||
|
uint32_t min[SMU_13_0_MAX_ODSETTING]; //default minimum settings
|
||||||
|
} __attribute__((packed));
|
||||||
|
|
||||||
|
enum SMU_13_0_PPCLOCK_ID {
|
||||||
|
SMU_13_0_PPCLOCK_GFXCLK = 0,
|
||||||
|
SMU_13_0_PPCLOCK_VCLK,
|
||||||
|
SMU_13_0_PPCLOCK_DCLK,
|
||||||
|
SMU_13_0_PPCLOCK_ECLK,
|
||||||
|
SMU_13_0_PPCLOCK_SOCCLK,
|
||||||
|
SMU_13_0_PPCLOCK_UCLK,
|
||||||
|
SMU_13_0_PPCLOCK_DCEFCLK,
|
||||||
|
SMU_13_0_PPCLOCK_DISPCLK,
|
||||||
|
SMU_13_0_PPCLOCK_PIXCLK,
|
||||||
|
SMU_13_0_PPCLOCK_PHYCLK,
|
||||||
|
SMU_13_0_PPCLOCK_COUNT,
|
||||||
|
};
|
||||||
|
#define SMU_13_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
|
||||||
|
|
||||||
|
struct smu_13_0_power_saving_clock_table {
|
||||||
|
uint8_t revision; //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION
|
||||||
|
uint8_t reserve[3]; //Zero filled field reserved for future use
|
||||||
|
uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
|
||||||
|
uint32_t max[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
|
||||||
|
uint32_t min[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
|
||||||
|
} __attribute__((packed));
|
||||||
|
|
||||||
|
struct smu_13_0_powerplay_table {
|
||||||
|
struct atom_common_table_header header;
|
||||||
|
uint8_t table_revision;
|
||||||
|
uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size
|
||||||
|
uint32_t golden_pp_id;
|
||||||
|
uint32_t golden_revision;
|
||||||
|
uint16_t format_id;
|
||||||
|
uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps
|
||||||
|
|
||||||
|
uint8_t thermal_controller_type; //one of SMU_13_0_PP_THERMALCONTROLLER
|
||||||
|
|
||||||
|
uint16_t small_power_limit1;
|
||||||
|
uint16_t small_power_limit2;
|
||||||
|
uint16_t boost_power_limit;
|
||||||
|
uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning.
|
||||||
|
uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
|
||||||
|
uint16_t software_shutdown_temp;
|
||||||
|
|
||||||
|
uint16_t reserve[6]; //Zero filled field reserved for future use
|
||||||
|
|
||||||
|
struct smu_13_0_power_saving_clock_table power_saving_clock;
|
||||||
|
struct smu_13_0_overdrive_table overdrive_table;
|
||||||
|
|
||||||
|
#ifndef SMU_13_0_PARTIAL_PPTABLE
|
||||||
|
PPTable_t smc_pptable; //PPTable_t in driver_if.h
|
||||||
|
#endif
|
||||||
|
} __attribute__((packed));
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -22,7 +22,7 @@
|
||||||
|
|
||||||
AMD_SWSMU_PATH = ../pm/swsmu
|
AMD_SWSMU_PATH = ../pm/swsmu
|
||||||
|
|
||||||
SWSMU_LIBS = smu11 smu12
|
SWSMU_LIBS = smu11 smu12 smu13
|
||||||
|
|
||||||
AMD_SWSMU = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/pm/swsmu/,$(SWSMU_LIBS)))
|
AMD_SWSMU = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/pm/swsmu/,$(SWSMU_LIBS)))
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -34,6 +34,7 @@
|
||||||
#include "sienna_cichlid_ppt.h"
|
#include "sienna_cichlid_ppt.h"
|
||||||
#include "renoir_ppt.h"
|
#include "renoir_ppt.h"
|
||||||
#include "vangogh_ppt.h"
|
#include "vangogh_ppt.h"
|
||||||
|
#include "aldebaran_ppt.h"
|
||||||
#include "amd_pcie.h"
|
#include "amd_pcie.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -555,6 +556,11 @@ static int smu_set_funcs(struct amdgpu_device *adev)
|
||||||
case CHIP_DIMGREY_CAVEFISH:
|
case CHIP_DIMGREY_CAVEFISH:
|
||||||
sienna_cichlid_set_ppt_funcs(smu);
|
sienna_cichlid_set_ppt_funcs(smu);
|
||||||
break;
|
break;
|
||||||
|
case CHIP_ALDEBARAN:
|
||||||
|
aldebaran_set_ppt_funcs(smu);
|
||||||
|
/* OD is not supported on Aldebaran */
|
||||||
|
smu->od_enabled = false;
|
||||||
|
break;
|
||||||
case CHIP_RENOIR:
|
case CHIP_RENOIR:
|
||||||
renoir_set_ppt_funcs(smu);
|
renoir_set_ppt_funcs(smu);
|
||||||
break;
|
break;
|
||||||
|
|
@ -2071,6 +2077,15 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block =
|
||||||
.funcs = &smu_ip_funcs,
|
.funcs = &smu_ip_funcs,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
const struct amdgpu_ip_block_version smu_v13_0_ip_block =
|
||||||
|
{
|
||||||
|
.type = AMD_IP_BLOCK_TYPE_SMC,
|
||||||
|
.major = 13,
|
||||||
|
.minor = 0,
|
||||||
|
.rev = 0,
|
||||||
|
.funcs = &smu_ip_funcs,
|
||||||
|
};
|
||||||
|
|
||||||
int smu_load_microcode(struct smu_context *smu)
|
int smu_load_microcode(struct smu_context *smu)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
|
||||||
30
drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
Normal file
30
drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
Normal file
|
|
@ -0,0 +1,30 @@
|
||||||
|
#
|
||||||
|
# Copyright 2020 Advanced Micro Devices, Inc.
|
||||||
|
#
|
||||||
|
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
# copy of this software and associated documentation files (the "Software"),
|
||||||
|
# to deal in the Software without restriction, including without limitation
|
||||||
|
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
# and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
# Software is furnished to do so, subject to the following conditions:
|
||||||
|
#
|
||||||
|
# The above copyright notice and this permission notice shall be included in
|
||||||
|
# all copies or substantial portions of the Software.
|
||||||
|
#
|
||||||
|
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
# OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
#
|
||||||
|
#
|
||||||
|
# Makefile for the 'smu manager' sub-component of powerplay.
|
||||||
|
# It provides the smu management services for the driver.
|
||||||
|
|
||||||
|
SMU13_MGR = smu_v13_0.o aldebaran_ppt.o
|
||||||
|
|
||||||
|
AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR))
|
||||||
|
|
||||||
|
AMD_POWERPLAY_FILES += $(AMD_SWSMU_SMU13MGR)
|
||||||
1317
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
Normal file
1317
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
Normal file
File diff suppressed because it is too large
Load diff
72
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h
Normal file
72
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h
Normal file
|
|
@ -0,0 +1,72 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef __ALDEBARAN_PPT_H__
|
||||||
|
#define __ALDEBARAN_PPT_H__
|
||||||
|
|
||||||
|
#define ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL 0x3
|
||||||
|
#define ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL 0x3
|
||||||
|
#define ALDEBARAN_UMD_PSTATE_MCLK_LEVEL 0x2
|
||||||
|
|
||||||
|
#define MAX_DPM_NUMBER 16
|
||||||
|
#define MAX_PCIE_CONF 2
|
||||||
|
|
||||||
|
struct aldebaran_dpm_level {
|
||||||
|
bool enabled;
|
||||||
|
uint32_t value;
|
||||||
|
uint32_t param1;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aldebaran_dpm_state {
|
||||||
|
uint32_t soft_min_level;
|
||||||
|
uint32_t soft_max_level;
|
||||||
|
uint32_t hard_min_level;
|
||||||
|
uint32_t hard_max_level;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aldebaran_single_dpm_table {
|
||||||
|
uint32_t count;
|
||||||
|
struct aldebaran_dpm_state dpm_state;
|
||||||
|
struct aldebaran_dpm_level dpm_levels[MAX_DPM_NUMBER];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aldebaran_pcie_table {
|
||||||
|
uint16_t count;
|
||||||
|
uint8_t pcie_gen[MAX_PCIE_CONF];
|
||||||
|
uint8_t pcie_lane[MAX_PCIE_CONF];
|
||||||
|
uint32_t lclk[MAX_PCIE_CONF];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aldebaran_dpm_table {
|
||||||
|
struct aldebaran_single_dpm_table soc_table;
|
||||||
|
struct aldebaran_single_dpm_table gfx_table;
|
||||||
|
struct aldebaran_single_dpm_table mem_table;
|
||||||
|
struct aldebaran_single_dpm_table eclk_table;
|
||||||
|
struct aldebaran_single_dpm_table vclk_table;
|
||||||
|
struct aldebaran_single_dpm_table dclk_table;
|
||||||
|
struct aldebaran_single_dpm_table fclk_table;
|
||||||
|
struct aldebaran_pcie_table pcie_table;
|
||||||
|
};
|
||||||
|
|
||||||
|
extern void aldebaran_set_ppt_funcs(struct smu_context *smu);
|
||||||
|
|
||||||
|
#endif
|
||||||
1790
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
Normal file
1790
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Reference in a new issue