drm/amd: Convert amdgpu to use suballocation helper.
Now that we have a generic suballocation helper, Use it in amdgpu. For lines that get moved or changed, also fix up pre-existing style issues. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230224095152.30134-3-thomas.hellstrom@linux.intel.com
This commit is contained in:
Maarten Lankhorst
Thomas Hellström
parent
849ee8a2f0
commit
c103a23f2f
6 changed files with 47 additions and 339 deletions
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@ -18,6 +18,7 @@ config DRM_AMDGPU
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select BACKLIGHT_CLASS_DEVICE
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select INTERVAL_TREE
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select DRM_BUDDY
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select DRM_SUBALLOC_HELPER
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# amdgpu depends on ACPI_VIDEO when ACPI is enabled, for select to work
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# ACPI_VIDEO's dependencies must also be selected.
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select INPUT if ACPI
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@ -423,29 +423,11 @@ struct amdgpu_clock {
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* alignment).
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*/
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#define AMDGPU_SA_NUM_FENCE_LISTS 32
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struct amdgpu_sa_manager {
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wait_queue_head_t wq;
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struct amdgpu_bo *bo;
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struct list_head *hole;
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struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
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struct list_head olist;
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unsigned size;
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uint64_t gpu_addr;
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void *cpu_ptr;
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uint32_t domain;
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uint32_t align;
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};
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/* sub-allocation buffer */
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struct amdgpu_sa_bo {
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struct list_head olist;
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struct list_head flist;
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struct amdgpu_sa_manager *manager;
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unsigned soffset;
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unsigned eoffset;
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struct dma_fence *fence;
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struct drm_suballoc_manager base;
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struct amdgpu_bo *bo;
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uint64_t gpu_addr;
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void *cpu_ptr;
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};
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int amdgpu_fence_slab_init(void);
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@ -69,7 +69,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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if (size) {
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r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type],
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&ib->sa_bo, size, 256);
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&ib->sa_bo, size);
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if (r) {
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dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
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return r;
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@ -309,8 +309,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
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for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
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r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i],
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AMDGPU_IB_POOL_SIZE,
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AMDGPU_GPU_PAGE_SIZE,
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AMDGPU_IB_POOL_SIZE, 256,
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AMDGPU_GEM_DOMAIN_GTT);
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if (r)
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goto error;
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@ -336,15 +336,22 @@ uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
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/*
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* sub allocation
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*/
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static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
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static inline struct amdgpu_sa_manager *
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to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
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{
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return sa_bo->manager->gpu_addr + sa_bo->soffset;
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return container_of(manager, struct amdgpu_sa_manager, base);
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}
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static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
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static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
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{
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return sa_bo->manager->cpu_ptr + sa_bo->soffset;
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return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
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drm_suballoc_soffset(sa_bo);
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}
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static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
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{
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return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
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drm_suballoc_soffset(sa_bo);
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}
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int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
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@ -355,11 +362,11 @@ void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
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int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
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struct amdgpu_sa_bo **sa_bo,
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unsigned size, unsigned align);
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struct drm_suballoc **sa_bo,
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unsigned int size);
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void amdgpu_sa_bo_free(struct amdgpu_device *adev,
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struct amdgpu_sa_bo **sa_bo,
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struct dma_fence *fence);
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struct drm_suballoc **sa_bo,
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struct dma_fence *fence);
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#if defined(CONFIG_DEBUG_FS)
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void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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struct seq_file *m);
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@ -27,6 +27,7 @@
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#include <drm/amdgpu_drm.h>
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#include <drm/gpu_scheduler.h>
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#include <drm/drm_print.h>
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#include <drm/drm_suballoc.h>
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struct amdgpu_device;
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struct amdgpu_ring;
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@ -92,7 +93,7 @@ enum amdgpu_ib_pool_type {
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};
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struct amdgpu_ib {
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struct amdgpu_sa_bo *sa_bo;
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struct drm_suballoc *sa_bo;
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uint32_t length_dw;
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uint64_t gpu_addr;
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uint32_t *ptr;
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@ -44,327 +44,63 @@
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#include "amdgpu.h"
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static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo);
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static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager,
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unsigned size, u32 align, u32 domain)
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unsigned int size, u32 suballoc_align, u32 domain)
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{
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int i, r;
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int r;
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init_waitqueue_head(&sa_manager->wq);
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sa_manager->bo = NULL;
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sa_manager->size = size;
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sa_manager->domain = domain;
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sa_manager->align = align;
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sa_manager->hole = &sa_manager->olist;
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INIT_LIST_HEAD(&sa_manager->olist);
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
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INIT_LIST_HEAD(&sa_manager->flist[i]);
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r = amdgpu_bo_create_kernel(adev, size, align, domain, &sa_manager->bo,
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&sa_manager->gpu_addr, &sa_manager->cpu_ptr);
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r = amdgpu_bo_create_kernel(adev, size, AMDGPU_GPU_PAGE_SIZE, domain,
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&sa_manager->bo, &sa_manager->gpu_addr,
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&sa_manager->cpu_ptr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
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return r;
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}
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memset(sa_manager->cpu_ptr, 0, sa_manager->size);
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memset(sa_manager->cpu_ptr, 0, size);
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drm_suballoc_manager_init(&sa_manager->base, size, suballoc_align);
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return r;
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}
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void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager)
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{
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struct amdgpu_sa_bo *sa_bo, *tmp;
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if (sa_manager->bo == NULL) {
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dev_err(adev->dev, "no bo for sa manager\n");
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return;
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}
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if (!list_empty(&sa_manager->olist)) {
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sa_manager->hole = &sa_manager->olist,
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amdgpu_sa_bo_try_free(sa_manager);
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if (!list_empty(&sa_manager->olist)) {
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dev_err(adev->dev, "sa_manager is not empty, clearing anyway\n");
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}
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}
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list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {
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amdgpu_sa_bo_remove_locked(sa_bo);
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}
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drm_suballoc_manager_fini(&sa_manager->base);
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amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr);
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sa_manager->size = 0;
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}
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static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo)
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{
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struct amdgpu_sa_manager *sa_manager = sa_bo->manager;
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if (sa_manager->hole == &sa_bo->olist) {
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sa_manager->hole = sa_bo->olist.prev;
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}
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list_del_init(&sa_bo->olist);
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list_del_init(&sa_bo->flist);
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dma_fence_put(sa_bo->fence);
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kfree(sa_bo);
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}
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static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager)
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{
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struct amdgpu_sa_bo *sa_bo, *tmp;
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if (sa_manager->hole->next == &sa_manager->olist)
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return;
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sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist);
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list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) {
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if (sa_bo->fence == NULL ||
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!dma_fence_is_signaled(sa_bo->fence)) {
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return;
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}
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amdgpu_sa_bo_remove_locked(sa_bo);
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}
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}
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static inline unsigned amdgpu_sa_bo_hole_soffset(struct amdgpu_sa_manager *sa_manager)
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{
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struct list_head *hole = sa_manager->hole;
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if (hole != &sa_manager->olist) {
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return list_entry(hole, struct amdgpu_sa_bo, olist)->eoffset;
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}
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return 0;
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}
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static inline unsigned amdgpu_sa_bo_hole_eoffset(struct amdgpu_sa_manager *sa_manager)
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{
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struct list_head *hole = sa_manager->hole;
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if (hole->next != &sa_manager->olist) {
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return list_entry(hole->next, struct amdgpu_sa_bo, olist)->soffset;
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}
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return sa_manager->size;
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}
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static bool amdgpu_sa_bo_try_alloc(struct amdgpu_sa_manager *sa_manager,
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struct amdgpu_sa_bo *sa_bo,
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unsigned size, unsigned align)
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{
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unsigned soffset, eoffset, wasted;
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soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
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eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
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wasted = (align - (soffset % align)) % align;
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if ((eoffset - soffset) >= (size + wasted)) {
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soffset += wasted;
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sa_bo->manager = sa_manager;
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sa_bo->soffset = soffset;
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sa_bo->eoffset = soffset + size;
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list_add(&sa_bo->olist, sa_manager->hole);
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INIT_LIST_HEAD(&sa_bo->flist);
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sa_manager->hole = &sa_bo->olist;
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return true;
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}
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return false;
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}
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/**
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* amdgpu_sa_event - Check if we can stop waiting
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*
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* @sa_manager: pointer to the sa_manager
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* @size: number of bytes we want to allocate
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* @align: alignment we need to match
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*
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* Check if either there is a fence we can wait for or
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* enough free memory to satisfy the allocation directly
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*/
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static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager,
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unsigned size, unsigned align)
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{
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unsigned soffset, eoffset, wasted;
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int i;
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
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if (!list_empty(&sa_manager->flist[i]))
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return true;
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soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
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eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
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wasted = (align - (soffset % align)) % align;
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if ((eoffset - soffset) >= (size + wasted)) {
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return true;
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}
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return false;
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}
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static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
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struct dma_fence **fences,
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unsigned *tries)
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{
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struct amdgpu_sa_bo *best_bo = NULL;
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unsigned i, soffset, best, tmp;
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/* if hole points to the end of the buffer */
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if (sa_manager->hole->next == &sa_manager->olist) {
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/* try again with its beginning */
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sa_manager->hole = &sa_manager->olist;
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return true;
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}
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soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
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/* to handle wrap around we add sa_manager->size */
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best = sa_manager->size * 2;
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/* go over all fence list and try to find the closest sa_bo
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* of the current last
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*/
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {
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struct amdgpu_sa_bo *sa_bo;
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fences[i] = NULL;
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if (list_empty(&sa_manager->flist[i]))
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continue;
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sa_bo = list_first_entry(&sa_manager->flist[i],
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struct amdgpu_sa_bo, flist);
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if (!dma_fence_is_signaled(sa_bo->fence)) {
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fences[i] = sa_bo->fence;
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continue;
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}
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/* limit the number of tries each ring gets */
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if (tries[i] > 2) {
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continue;
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}
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tmp = sa_bo->soffset;
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if (tmp < soffset) {
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/* wrap around, pretend it's after */
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tmp += sa_manager->size;
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}
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tmp -= soffset;
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if (tmp < best) {
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/* this sa bo is the closest one */
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best = tmp;
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best_bo = sa_bo;
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}
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}
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if (best_bo) {
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uint32_t idx = best_bo->fence->context;
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idx %= AMDGPU_SA_NUM_FENCE_LISTS;
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++tries[idx];
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sa_manager->hole = best_bo->olist.prev;
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/* we knew that this one is signaled,
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so it's save to remote it */
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amdgpu_sa_bo_remove_locked(best_bo);
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return true;
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}
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return false;
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}
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int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
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struct amdgpu_sa_bo **sa_bo,
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unsigned size, unsigned align)
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struct drm_suballoc **sa_bo,
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unsigned int size)
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{
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struct dma_fence *fences[AMDGPU_SA_NUM_FENCE_LISTS];
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unsigned tries[AMDGPU_SA_NUM_FENCE_LISTS];
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unsigned count;
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int i, r;
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signed long t;
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struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size,
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GFP_KERNEL, true, 0);
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if (WARN_ON_ONCE(align > sa_manager->align))
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return -EINVAL;
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if (IS_ERR(sa)) {
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*sa_bo = NULL;
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if (WARN_ON_ONCE(size > sa_manager->size))
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return -EINVAL;
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return PTR_ERR(sa);
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}
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*sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
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if (!(*sa_bo))
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return -ENOMEM;
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(*sa_bo)->manager = sa_manager;
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(*sa_bo)->fence = NULL;
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INIT_LIST_HEAD(&(*sa_bo)->olist);
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INIT_LIST_HEAD(&(*sa_bo)->flist);
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spin_lock(&sa_manager->wq.lock);
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do {
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
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tries[i] = 0;
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do {
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amdgpu_sa_bo_try_free(sa_manager);
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if (amdgpu_sa_bo_try_alloc(sa_manager, *sa_bo,
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size, align)) {
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spin_unlock(&sa_manager->wq.lock);
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return 0;
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}
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/* see if we can skip over some allocations */
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} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
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for (i = 0, count = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
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if (fences[i])
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fences[count++] = dma_fence_get(fences[i]);
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if (count) {
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spin_unlock(&sa_manager->wq.lock);
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t = dma_fence_wait_any_timeout(fences, count, false,
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MAX_SCHEDULE_TIMEOUT,
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NULL);
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for (i = 0; i < count; ++i)
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dma_fence_put(fences[i]);
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r = (t > 0) ? 0 : t;
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spin_lock(&sa_manager->wq.lock);
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} else {
|
||||
/* if we have nothing to wait for block */
|
||||
r = wait_event_interruptible_locked(
|
||||
sa_manager->wq,
|
||||
amdgpu_sa_event(sa_manager, size, align)
|
||||
);
|
||||
}
|
||||
|
||||
} while (!r);
|
||||
|
||||
spin_unlock(&sa_manager->wq.lock);
|
||||
kfree(*sa_bo);
|
||||
*sa_bo = NULL;
|
||||
return r;
|
||||
*sa_bo = sa;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
|
||||
void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct drm_suballoc **sa_bo,
|
||||
struct dma_fence *fence)
|
||||
{
|
||||
struct amdgpu_sa_manager *sa_manager;
|
||||
|
||||
if (sa_bo == NULL || *sa_bo == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
sa_manager = (*sa_bo)->manager;
|
||||
spin_lock(&sa_manager->wq.lock);
|
||||
if (fence && !dma_fence_is_signaled(fence)) {
|
||||
uint32_t idx;
|
||||
|
||||
(*sa_bo)->fence = dma_fence_get(fence);
|
||||
idx = fence->context % AMDGPU_SA_NUM_FENCE_LISTS;
|
||||
list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]);
|
||||
} else {
|
||||
amdgpu_sa_bo_remove_locked(*sa_bo);
|
||||
}
|
||||
wake_up_all_locked(&sa_manager->wq);
|
||||
spin_unlock(&sa_manager->wq.lock);
|
||||
drm_suballoc_free(*sa_bo, fence);
|
||||
*sa_bo = NULL;
|
||||
}
|
||||
|
||||
|
|
@ -373,26 +109,8 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
|
|||
void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
|
||||
struct seq_file *m)
|
||||
{
|
||||
struct amdgpu_sa_bo *i;
|
||||
struct drm_printer p = drm_seq_file_printer(m);
|
||||
|
||||
spin_lock(&sa_manager->wq.lock);
|
||||
list_for_each_entry(i, &sa_manager->olist, olist) {
|
||||
uint64_t soffset = i->soffset + sa_manager->gpu_addr;
|
||||
uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
|
||||
if (&i->olist == sa_manager->hole) {
|
||||
seq_printf(m, ">");
|
||||
} else {
|
||||
seq_printf(m, " ");
|
||||
}
|
||||
seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
|
||||
soffset, eoffset, eoffset - soffset);
|
||||
|
||||
if (i->fence)
|
||||
seq_printf(m, " protected by 0x%016llx on context %llu",
|
||||
i->fence->seqno, i->fence->context);
|
||||
|
||||
seq_printf(m, "\n");
|
||||
}
|
||||
spin_unlock(&sa_manager->wq.lock);
|
||||
drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue