drm/msm/disp/dpu1: Add support for DSC
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add support by adding hw blocks for DSC Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/480912/ Link: https://lore.kernel.org/r/20220406094031.1027376-4-vkoul@kernel.org [DB: applied typo noticed by Robert Foss] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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5 changed files with 322 additions and 0 deletions
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@ -63,6 +63,7 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
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disp/dpu1/dpu_formats.o \
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disp/dpu1/dpu_hw_catalog.o \
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disp/dpu1/dpu_hw_ctl.o \
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disp/dpu1/dpu_hw_dsc.o \
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disp/dpu1/dpu_hw_interrupts.o \
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disp/dpu1/dpu_hw_intf.o \
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disp/dpu1/dpu_hw_lm.o \
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@ -561,6 +561,16 @@ struct dpu_merge_3d_cfg {
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const struct dpu_merge_3d_sub_blks *sblk;
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};
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/**
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* struct dpu_dsc_cfg - information of DSC blocks
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* @id enum identifying this block
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* @base register offset of this block
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* @features bit mask identifying sub-blocks/features
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*/
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struct dpu_dsc_cfg {
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DPU_HW_BLK_INFO;
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};
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/**
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* struct dpu_intf_cfg - information of timing engine blocks
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* @id enum identifying this block
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@ -757,6 +767,9 @@ struct dpu_mdss_cfg {
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u32 merge_3d_count;
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const struct dpu_merge_3d_cfg *merge_3d;
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u32 dsc_count;
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struct dpu_dsc_cfg *dsc;
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u32 intf_count;
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const struct dpu_intf_cfg *intf;
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215
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
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215
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
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@ -0,0 +1,215 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020-2022, Linaro Limited
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*/
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#include "dpu_kms.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hwio.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_dsc.h"
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#define DSC_COMMON_MODE 0x000
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#define DSC_ENC 0x004
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#define DSC_PICTURE 0x008
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#define DSC_SLICE 0x00C
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#define DSC_CHUNK_SIZE 0x010
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#define DSC_DELAY 0x014
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#define DSC_SCALE_INITIAL 0x018
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#define DSC_SCALE_DEC_INTERVAL 0x01C
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#define DSC_SCALE_INC_INTERVAL 0x020
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#define DSC_FIRST_LINE_BPG_OFFSET 0x024
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#define DSC_BPG_OFFSET 0x028
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#define DSC_DSC_OFFSET 0x02C
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#define DSC_FLATNESS 0x030
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#define DSC_RC_MODEL_SIZE 0x034
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#define DSC_RC 0x038
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#define DSC_RC_BUF_THRESH 0x03C
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#define DSC_RANGE_MIN_QP 0x074
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#define DSC_RANGE_MAX_QP 0x0B0
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#define DSC_RANGE_BPG_OFFSET 0x0EC
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static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
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{
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struct dpu_hw_blk_reg_map *c = &dsc->hw;
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DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
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}
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static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
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struct msm_display_dsc_config *dsc,
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u32 mode,
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u32 initial_lines)
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{
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struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
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u32 data, lsb, bpp;
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u32 slice_last_group_size;
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u32 det_thresh_flatness;
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bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
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DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
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if (is_cmd_mode)
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initial_lines += 1;
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slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
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data = (initial_lines << 20);
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data |= ((slice_last_group_size - 1) << 18);
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/* bpp is 6.4 format, 4 LSBs bits are for fractional part */
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data |= dsc->drm->bits_per_pixel << 12;
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lsb = dsc->drm->bits_per_pixel % 4;
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bpp = dsc->drm->bits_per_pixel / 4;
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bpp *= 4;
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bpp <<= 4;
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bpp |= lsb;
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data |= bpp << 8;
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data |= (dsc->drm->block_pred_enable << 7);
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data |= (dsc->drm->line_buf_depth << 3);
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data |= (dsc->drm->simple_422 << 2);
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data |= (dsc->drm->convert_rgb << 1);
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data |= dsc->drm->bits_per_component;
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DPU_REG_WRITE(c, DSC_ENC, data);
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data = dsc->drm->pic_width << 16;
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data |= dsc->drm->pic_height;
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DPU_REG_WRITE(c, DSC_PICTURE, data);
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data = dsc->drm->slice_width << 16;
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data |= dsc->drm->slice_height;
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DPU_REG_WRITE(c, DSC_SLICE, data);
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data = dsc->drm->slice_chunk_size << 16;
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DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
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data = dsc->drm->initial_dec_delay << 16;
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data |= dsc->drm->initial_xmit_delay;
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DPU_REG_WRITE(c, DSC_DELAY, data);
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data = dsc->drm->initial_scale_value;
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DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
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data = dsc->drm->scale_decrement_interval;
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DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
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data = dsc->drm->scale_increment_interval;
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DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
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data = dsc->drm->first_line_bpg_offset;
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DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
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data = dsc->drm->nfl_bpg_offset << 16;
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data |= dsc->drm->slice_bpg_offset;
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DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
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data = dsc->drm->initial_offset << 16;
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data |= dsc->drm->final_offset;
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DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
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det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
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data = det_thresh_flatness << 10;
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data |= dsc->drm->flatness_max_qp << 5;
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data |= dsc->drm->flatness_min_qp;
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DPU_REG_WRITE(c, DSC_FLATNESS, data);
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data = dsc->drm->rc_model_size;
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DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
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data = dsc->drm->rc_tgt_offset_low << 18;
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data |= dsc->drm->rc_tgt_offset_high << 14;
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data |= dsc->drm->rc_quant_incr_limit1 << 9;
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data |= dsc->drm->rc_quant_incr_limit0 << 4;
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data |= dsc->drm->rc_edge_factor;
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DPU_REG_WRITE(c, DSC_RC, data);
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}
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static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
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struct msm_display_dsc_config *dsc)
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{
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struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
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struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
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u32 off;
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int i;
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off = DSC_RC_BUF_THRESH;
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for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
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DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
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off += 4;
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}
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off = DSC_RANGE_MIN_QP;
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for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
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DPU_REG_WRITE(c, off, rc[i].range_min_qp);
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off += 4;
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}
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off = DSC_RANGE_MAX_QP;
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for (i = 0; i < 15; i++) {
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DPU_REG_WRITE(c, off, rc[i].range_max_qp);
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off += 4;
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}
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off = DSC_RANGE_BPG_OFFSET;
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for (i = 0; i < 15; i++) {
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DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
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off += 4;
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}
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}
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static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
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struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->dsc_count; i++) {
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if (dsc == m->dsc[i].id) {
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b->base_off = addr;
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b->blk_off = m->dsc[i].base;
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b->length = m->dsc[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_DSC;
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return &m->dsc[i];
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}
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}
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return NULL;
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}
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static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
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unsigned long cap)
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{
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ops->dsc_disable = dpu_hw_dsc_disable;
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ops->dsc_config = dpu_hw_dsc_config;
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ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
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};
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struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
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struct dpu_mdss_cfg *m)
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{
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struct dpu_hw_dsc *c;
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struct dpu_dsc_cfg *cfg;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _dsc_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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c->idx = idx;
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c->caps = cfg;
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_setup_dsc_ops(&c->ops, c->caps->features);
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return c;
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}
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void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
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{
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kfree(dsc);
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}
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80
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
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80
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2020-2022, Linaro Limited */
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#ifndef _DPU_HW_DSC_H
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#define _DPU_HW_DSC_H
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#include <drm/drm_dsc.h>
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#define DSC_MODE_SPLIT_PANEL BIT(0)
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#define DSC_MODE_MULTIPLEX BIT(1)
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#define DSC_MODE_VIDEO BIT(2)
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struct dpu_hw_dsc;
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/**
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* struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct dpu_hw_dsc_ops {
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/**
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* dsc_disable - disable dsc
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* @hw_dsc: Pointer to dsc context
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*/
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void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
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/**
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* dsc_config - configures dsc encoder
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* @hw_dsc: Pointer to dsc context
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* @dsc: panel dsc parameters
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* @mode: dsc topology mode to be set
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* @initial_lines: amount of initial lines to be used
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*/
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void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
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struct msm_display_dsc_config *dsc,
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u32 mode,
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u32 initial_lines);
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/**
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* dsc_config_thresh - programs panel thresholds
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* @hw_dsc: Pointer to dsc context
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* @dsc: panel dsc parameters
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*/
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void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
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struct msm_display_dsc_config *dsc);
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};
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struct dpu_hw_dsc {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* dsc */
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enum dpu_dsc idx;
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const struct dpu_dsc_cfg *caps;
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/* ops */
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struct dpu_hw_dsc_ops ops;
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};
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/**
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* dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
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* @idx: DSC index for which driver object is required
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* @addr: Mapped register io address of MDP
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* @m: Pointer to mdss catalog data
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* Returns: Error code or allocated dpu_hw_dsc context
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*/
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struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
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struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_dsc_destroy - destroys dsc driver context
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* @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
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*/
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void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
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static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_dsc, base);
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}
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#endif /* _DPU_HW_DSC_H */
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@ -97,6 +97,7 @@ enum dpu_hw_blk_type {
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DPU_HW_BLK_WB,
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DPU_HW_BLK_DSPP,
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DPU_HW_BLK_MERGE_3D,
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DPU_HW_BLK_DSC,
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DPU_HW_BLK_MAX,
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};
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CTL_MAX
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};
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enum dpu_dsc {
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DSC_NONE = 0,
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DSC_0,
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DSC_1,
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DSC_2,
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DSC_3,
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DSC_4,
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DSC_5,
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DSC_MAX
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};
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enum dpu_pingpong {
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PINGPONG_0 = 1,
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PINGPONG_1,
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#define DPU_DBG_MASK_VBIF (1 << 8)
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#define DPU_DBG_MASK_ROT (1 << 9)
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#define DPU_DBG_MASK_DSPP (1 << 10)
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#define DPU_DBG_MASK_DSC (1 << 11)
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#endif /* _DPU_HW_MDSS_H */
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