drm/msm/dp: Add basic PSR support for eDP
Add support for basic panel self refresh (PSR) feature for eDP. Add a new interface to set PSR state in the sink from DPU. Program the eDP controller to issue PSR enter and exit SDP to the sink. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524734/ Link: https://lore.kernel.org/r/1677774797-31063-10-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Vinod Polimera
Dmitry Baryshkov
parent
cdfd0e6246
commit
cd779808cc
11 changed files with 411 additions and 1 deletions
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@ -47,6 +47,14 @@
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#define DP_INTERRUPT_STATUS2_MASK \
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(DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
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#define DP_INTERRUPT_STATUS4 \
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(PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \
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PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT)
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#define DP_INTERRUPT_MASK4 \
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(PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
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PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
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struct dp_catalog_private {
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struct device *dev;
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struct drm_device *drm_dev;
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@ -359,6 +367,23 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog)
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ln_mapping);
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}
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void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog,
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bool enable)
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{
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u32 val;
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struct dp_catalog_private *catalog = container_of(dp_catalog,
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struct dp_catalog_private, dp_catalog);
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val = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
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if (enable)
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val |= DP_MAINLINK_CTRL_ENABLE;
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else
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val &= ~DP_MAINLINK_CTRL_ENABLE;
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dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val);
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}
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void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
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bool enable)
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{
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@ -610,6 +635,47 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
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dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
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}
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static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
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{
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/* trigger sdp */
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dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP);
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dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0);
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}
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void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog)
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{
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struct dp_catalog_private *catalog = container_of(dp_catalog,
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struct dp_catalog_private, dp_catalog);
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u32 config;
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/* enable PSR1 function */
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config = dp_read_link(catalog, REG_PSR_CONFIG);
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config |= PSR1_SUPPORTED;
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dp_write_link(catalog, REG_PSR_CONFIG, config);
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dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
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dp_catalog_enable_sdp(catalog);
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}
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void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter)
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{
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struct dp_catalog_private *catalog = container_of(dp_catalog,
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struct dp_catalog_private, dp_catalog);
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u32 cmd;
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cmd = dp_read_link(catalog, REG_PSR_CMD);
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cmd &= ~(PSR_ENTER | PSR_EXIT);
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if (enter)
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cmd |= PSR_ENTER;
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else
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cmd |= PSR_EXIT;
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dp_catalog_enable_sdp(catalog);
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dp_write_link(catalog, REG_PSR_CMD, cmd);
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}
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u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
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{
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struct dp_catalog_private *catalog = container_of(dp_catalog,
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@ -645,6 +711,20 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
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return isr & (mask | ~DP_DP_HPD_INT_MASK);
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}
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u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog)
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{
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struct dp_catalog_private *catalog = container_of(dp_catalog,
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struct dp_catalog_private, dp_catalog);
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u32 intr, intr_ack;
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intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4);
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intr_ack = (intr & DP_INTERRUPT_STATUS4)
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<< DP_INTERRUPT_STATUS_ACK_SHIFT;
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dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack);
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return intr;
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}
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int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
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{
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struct dp_catalog_private *catalog = container_of(dp_catalog,
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@ -93,6 +93,7 @@ void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
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void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
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void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
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void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
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void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
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void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
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void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
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u32 stream_rate_khz, bool fixed_nvid);
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@ -104,12 +105,15 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
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void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
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u32 intr_mask, bool en);
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void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog);
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void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog);
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void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter);
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u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
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u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
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void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
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int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
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u8 p_level);
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int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
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u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog);
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void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
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u32 dp_tu, u32 valid_boundary,
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u32 valid_boundary2);
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@ -22,6 +22,7 @@
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#define DP_KHZ_TO_HZ 1000
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#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
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#define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
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#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
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#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
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@ -80,6 +81,7 @@ struct dp_ctrl_private {
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struct dp_catalog *catalog;
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struct completion idle_comp;
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struct completion psr_op_comp;
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struct completion video_comp;
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};
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@ -153,6 +155,9 @@ static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
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config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
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config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
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if (ctrl->panel->psr_cap.version)
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config |= DP_CONFIGURATION_CTRL_SEND_VSC;
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dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
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}
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@ -1375,6 +1380,64 @@ void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
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dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
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}
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void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl)
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{
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u8 cfg;
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struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
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struct dp_ctrl_private, dp_ctrl);
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if (!ctrl->panel->psr_cap.version)
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return;
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dp_catalog_ctrl_config_psr(ctrl->catalog);
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cfg = DP_PSR_ENABLE;
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drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1);
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}
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void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter)
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{
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struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
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struct dp_ctrl_private, dp_ctrl);
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if (!ctrl->panel->psr_cap.version)
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return;
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/*
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* When entering PSR,
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* 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT
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* 2. Turn off video
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* 3. Disable the mainlink
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*
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* When exiting PSR,
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* 1. Enable the mainlink
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* 2. Send the PSR exit SDP
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*/
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if (enter) {
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reinit_completion(&ctrl->psr_op_comp);
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dp_catalog_ctrl_set_psr(ctrl->catalog, true);
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if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
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PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
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DRM_ERROR("PSR_ENTRY timedout\n");
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dp_catalog_ctrl_set_psr(ctrl->catalog, false);
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return;
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}
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dp_ctrl_push_idle(dp_ctrl);
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dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
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dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
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} else {
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dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
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dp_catalog_ctrl_set_psr(ctrl->catalog, false);
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dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
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dp_ctrl_wait4video_ready(ctrl);
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dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
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}
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}
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void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
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{
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struct dp_ctrl_private *ctrl;
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@ -1989,6 +2052,22 @@ void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
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ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
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if (ctrl->panel->psr_cap.version) {
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isr = dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog);
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if (isr)
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complete(&ctrl->psr_op_comp);
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if (isr & PSR_EXIT_INT)
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drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n");
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if (isr & PSR_UPDATE_INT)
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drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n");
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if (isr & PSR_CAPTURE_INT)
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drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n");
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}
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isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
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if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
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@ -2035,6 +2114,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
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dev_err(dev, "failed to add DP OPP table\n");
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init_completion(&ctrl->idle_comp);
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init_completion(&ctrl->psr_op_comp);
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init_completion(&ctrl->video_comp);
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/* in parameters */
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@ -37,4 +37,7 @@ void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl);
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void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl);
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void dp_ctrl_irq_phy_exit(struct dp_ctrl *dp_ctrl);
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void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable);
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void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl);
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#endif /* _DP_CTRL_H_ */
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@ -406,6 +406,8 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp)
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edid = dp->panel->edid;
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dp->dp_display.psr_supported = dp->panel->psr_cap.version;
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dp->audio_supported = drm_detect_monitor_audio(edid);
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dp_panel_handle_sink_request(dp->panel);
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@ -910,6 +912,10 @@ static int dp_display_post_enable(struct msm_dp *dp_display)
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/* signal the connect event late to synchronize video and display */
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dp_display_handle_plugged_change(dp_display, true);
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if (dp_display->psr_supported)
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dp_ctrl_config_psr(dp->ctrl);
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return 0;
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}
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@ -1104,6 +1110,19 @@ static void dp_display_config_hpd(struct dp_display_private *dp)
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enable_irq(dp->irq);
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}
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void dp_display_set_psr(struct msm_dp *dp_display, bool enter)
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{
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struct dp_display_private *dp;
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if (!dp_display) {
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DRM_ERROR("invalid params\n");
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return;
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}
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dp = container_of(dp_display, struct dp_display_private, dp_display);
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dp_ctrl_set_psr(dp->ctrl, enter);
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}
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static int hpd_event_thread(void *data)
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{
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struct dp_display_private *dp_priv;
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@ -29,6 +29,7 @@ struct msm_dp {
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u32 max_dp_lanes;
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struct dp_audio *dp_audio;
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bool psr_supported;
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};
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int dp_display_set_plugged_cb(struct msm_dp *dp_display,
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@ -39,5 +40,6 @@ bool dp_display_check_video_test(struct msm_dp *dp_display);
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int dp_display_get_test_bpp(struct msm_dp *dp_display);
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void dp_display_signal_audio_start(struct msm_dp *dp_display);
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void dp_display_signal_audio_complete(struct msm_dp *dp_display);
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void dp_display_set_psr(struct msm_dp *dp, bool enter);
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#endif /* _DP_DISPLAY_H_ */
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@ -107,6 +107,137 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
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.hpd_notify = dp_bridge_hpd_notify,
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};
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static int edp_bridge_atomic_check(struct drm_bridge *drm_bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct msm_dp *dp = to_dp_bridge(drm_bridge)->dp_display;
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if (WARN_ON(!conn_state))
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return -ENODEV;
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if (!conn_state->crtc || !crtc_state)
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return 0;
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if (crtc_state->self_refresh_active && !dp->psr_supported)
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return -EINVAL;
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return 0;
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}
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static void edp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
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struct drm_bridge_state *old_bridge_state)
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{
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struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
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struct drm_crtc *crtc;
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struct drm_crtc_state *old_crtc_state;
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struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
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struct msm_dp *dp = dp_bridge->dp_display;
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/*
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* Check the old state of the crtc to determine if the panel
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* was put into psr state previously by the edp_bridge_atomic_disable.
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* If the panel is in psr, just exit psr state and skip the full
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* bridge enable sequence.
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*/
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crtc = drm_atomic_get_new_crtc_for_encoder(atomic_state,
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drm_bridge->encoder);
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if (!crtc)
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return;
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old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
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if (old_crtc_state && old_crtc_state->self_refresh_active) {
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dp_display_set_psr(dp, false);
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return;
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}
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dp_bridge_atomic_enable(drm_bridge, old_bridge_state);
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}
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static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
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struct drm_bridge_state *old_bridge_state)
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{
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struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
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struct drm_crtc *crtc;
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struct drm_crtc_state *new_crtc_state = NULL, *old_crtc_state = NULL;
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struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
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struct msm_dp *dp = dp_bridge->dp_display;
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crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state,
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drm_bridge->encoder);
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if (!crtc)
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goto out;
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new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
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if (!new_crtc_state)
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goto out;
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old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
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if (!old_crtc_state)
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goto out;
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/*
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* Set self refresh mode if current crtc state is active.
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*
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* If old crtc state is active, then this is a display disable
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* call while the sink is in psr state. So, exit psr here.
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* The eDP controller will be disabled in the
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* edp_bridge_atomic_post_disable function.
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*
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* We observed sink is stuck in self refresh if psr exit is skipped
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* when display disable occurs while the sink is in psr state.
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*/
|
||||
if (new_crtc_state->self_refresh_active) {
|
||||
dp_display_set_psr(dp, true);
|
||||
return;
|
||||
} else if (old_crtc_state->self_refresh_active) {
|
||||
dp_display_set_psr(dp, false);
|
||||
return;
|
||||
}
|
||||
|
||||
out:
|
||||
dp_bridge_atomic_disable(drm_bridge, old_bridge_state);
|
||||
}
|
||||
|
||||
static void edp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,
|
||||
struct drm_bridge_state *old_bridge_state)
|
||||
{
|
||||
struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_crtc_state *new_crtc_state = NULL;
|
||||
|
||||
crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state,
|
||||
drm_bridge->encoder);
|
||||
if (!crtc)
|
||||
return;
|
||||
|
||||
new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
|
||||
if (!new_crtc_state)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Self refresh mode is already set in edp_bridge_atomic_disable.
|
||||
*/
|
||||
if (new_crtc_state->self_refresh_active)
|
||||
return;
|
||||
|
||||
dp_bridge_atomic_post_disable(drm_bridge, old_bridge_state);
|
||||
}
|
||||
|
||||
static const struct drm_bridge_funcs edp_bridge_ops = {
|
||||
.atomic_enable = edp_bridge_atomic_enable,
|
||||
.atomic_disable = edp_bridge_atomic_disable,
|
||||
.atomic_post_disable = edp_bridge_atomic_post_disable,
|
||||
.mode_set = dp_bridge_mode_set,
|
||||
.mode_valid = dp_bridge_mode_valid,
|
||||
.atomic_reset = drm_atomic_helper_bridge_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
|
||||
.atomic_check = edp_bridge_atomic_check,
|
||||
};
|
||||
|
||||
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
|
||||
struct drm_encoder *encoder)
|
||||
{
|
||||
|
|
@ -121,7 +252,7 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *
|
|||
dp_bridge->dp_display = dp_display;
|
||||
|
||||
bridge = &dp_bridge->bridge;
|
||||
bridge->funcs = &dp_bridge_ops;
|
||||
bridge->funcs = dp_display->is_edp ? &edp_bridge_ops : &dp_bridge_ops;
|
||||
bridge->type = dp_display->connector_type;
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -937,6 +937,38 @@ static int dp_link_process_phy_test_pattern_request(
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool dp_link_read_psr_error_status(struct dp_link_private *link)
|
||||
{
|
||||
u8 status;
|
||||
|
||||
drm_dp_dpcd_read(link->aux, DP_PSR_ERROR_STATUS, &status, 1);
|
||||
|
||||
if (status & DP_PSR_LINK_CRC_ERROR)
|
||||
DRM_ERROR("PSR LINK CRC ERROR\n");
|
||||
else if (status & DP_PSR_RFB_STORAGE_ERROR)
|
||||
DRM_ERROR("PSR RFB STORAGE ERROR\n");
|
||||
else if (status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
|
||||
DRM_ERROR("PSR VSC SDP UNCORRECTABLE ERROR\n");
|
||||
else
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool dp_link_psr_capability_changed(struct dp_link_private *link)
|
||||
{
|
||||
u8 status;
|
||||
|
||||
drm_dp_dpcd_read(link->aux, DP_PSR_ESI, &status, 1);
|
||||
|
||||
if (status & DP_PSR_CAPS_CHANGE) {
|
||||
drm_dbg_dp(link->drm_dev, "PSR Capability Change\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
|
||||
{
|
||||
return link_status[r - DP_LANE0_1_STATUS];
|
||||
|
|
@ -1055,6 +1087,10 @@ int dp_link_process_request(struct dp_link *dp_link)
|
|||
dp_link->sink_request |= DP_TEST_LINK_TRAINING;
|
||||
} else if (!dp_link_process_phy_test_pattern_request(link)) {
|
||||
dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN;
|
||||
} else if (dp_link_read_psr_error_status(link)) {
|
||||
DRM_ERROR("PSR IRQ_HPD received\n");
|
||||
} else if (dp_link_psr_capability_changed(link)) {
|
||||
drm_dbg_dp(link->drm_dev, "PSR Capabiity changed");
|
||||
} else {
|
||||
ret = dp_link_process_link_status_update(link);
|
||||
if (!ret) {
|
||||
|
|
|
|||
|
|
@ -20,6 +20,27 @@ struct dp_panel_private {
|
|||
bool aux_cfg_update_done;
|
||||
};
|
||||
|
||||
static void dp_panel_read_psr_cap(struct dp_panel_private *panel)
|
||||
{
|
||||
ssize_t rlen;
|
||||
struct dp_panel *dp_panel;
|
||||
|
||||
dp_panel = &panel->dp_panel;
|
||||
|
||||
/* edp sink */
|
||||
if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
|
||||
rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT,
|
||||
&dp_panel->psr_cap, sizeof(dp_panel->psr_cap));
|
||||
if (rlen == sizeof(dp_panel->psr_cap)) {
|
||||
drm_dbg_dp(panel->drm_dev,
|
||||
"psr version: 0x%x, psr_cap: 0x%x\n",
|
||||
dp_panel->psr_cap.version,
|
||||
dp_panel->psr_cap.capabilities);
|
||||
} else
|
||||
DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen);
|
||||
}
|
||||
}
|
||||
|
||||
static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
|
||||
{
|
||||
int rc = 0;
|
||||
|
|
@ -107,6 +128,7 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
|
|||
}
|
||||
}
|
||||
|
||||
dp_panel_read_psr_cap(panel);
|
||||
end:
|
||||
return rc;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,6 +34,11 @@ struct dp_panel_in {
|
|||
struct dp_catalog *catalog;
|
||||
};
|
||||
|
||||
struct dp_panel_psr {
|
||||
u8 version;
|
||||
u8 capabilities;
|
||||
};
|
||||
|
||||
struct dp_panel {
|
||||
/* dpcd raw data */
|
||||
u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
|
||||
|
|
@ -46,6 +51,7 @@ struct dp_panel {
|
|||
struct edid *edid;
|
||||
struct drm_connector *connector;
|
||||
struct dp_display_mode dp_mode;
|
||||
struct dp_panel_psr psr_cap;
|
||||
bool video_test;
|
||||
|
||||
u32 vic;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,20 @@
|
|||
#define REG_DP_INTR_STATUS2 (0x00000024)
|
||||
#define REG_DP_INTR_STATUS3 (0x00000028)
|
||||
|
||||
#define REG_DP_INTR_STATUS4 (0x0000002C)
|
||||
#define PSR_UPDATE_INT (0x00000001)
|
||||
#define PSR_CAPTURE_INT (0x00000004)
|
||||
#define PSR_EXIT_INT (0x00000010)
|
||||
#define PSR_UPDATE_ERROR_INT (0x00000040)
|
||||
#define PSR_WAKE_ERROR_INT (0x00000100)
|
||||
|
||||
#define REG_DP_INTR_MASK4 (0x00000030)
|
||||
#define PSR_UPDATE_MASK (0x00000001)
|
||||
#define PSR_CAPTURE_MASK (0x00000002)
|
||||
#define PSR_EXIT_MASK (0x00000004)
|
||||
#define PSR_UPDATE_ERROR_MASK (0x00000008)
|
||||
#define PSR_WAKE_ERROR_MASK (0x00000010)
|
||||
|
||||
#define REG_DP_DP_HPD_CTRL (0x00000000)
|
||||
#define DP_DP_HPD_CTRL_HPD_EN (0x00000001)
|
||||
|
||||
|
|
@ -164,6 +178,16 @@
|
|||
#define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094)
|
||||
#define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098)
|
||||
|
||||
#define REG_PSR_CONFIG (0x00000100)
|
||||
#define DISABLE_PSR (0x00000000)
|
||||
#define PSR1_SUPPORTED (0x00000001)
|
||||
#define PSR2_WITHOUT_FRAMESYNC (0x00000002)
|
||||
#define PSR2_WITH_FRAMESYNC (0x00000003)
|
||||
|
||||
#define REG_PSR_CMD (0x00000110)
|
||||
#define PSR_ENTER (0x00000001)
|
||||
#define PSR_EXIT (0x00000002)
|
||||
|
||||
#define MMSS_DP_PSR_CRC_RG (0x00000154)
|
||||
#define MMSS_DP_PSR_CRC_B (0x00000158)
|
||||
|
||||
|
|
@ -184,6 +208,9 @@
|
|||
#define MMSS_DP_AUDIO_STREAM_0 (0x00000240)
|
||||
#define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
|
||||
|
||||
#define MMSS_DP_SDP_CFG3 (0x0000024c)
|
||||
#define UPDATE_SDP (0x00000001)
|
||||
|
||||
#define MMSS_DP_EXTENSION_0 (0x00000250)
|
||||
#define MMSS_DP_EXTENSION_1 (0x00000254)
|
||||
#define MMSS_DP_EXTENSION_2 (0x00000258)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue