riscv: dts: starfive: visionfive 2: correct spi's ss pin
The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.
Fixes: 74fb20c8f0
("riscv: dts: starfive: Add spi node and pins configuration")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
parent
1558209533
commit
cf98fe6b57
1 changed files with 1 additions and 1 deletions
|
@ -431,7 +431,7 @@
|
|||
};
|
||||
|
||||
ss-pins {
|
||||
pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
|
||||
pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
|
||||
GPOEN_ENABLE,
|
||||
GPI_SYS_SPI0_FSS)>;
|
||||
bias-disable;
|
||||
|
|
Loading…
Add table
Reference in a new issue