ath11k: enable DP interrupt setup for QCA6390
QCA6390 uses MSI interrupt, so need to configure msi_add and msi_data to dp srngs. As there are so many DP srngs, so need to group them. Each group shares one MSI interrupt. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597555891-26112-2-git-send-email-kvalo@codeaurora.org
This commit is contained in:
Carl Huang
Kalle Valo
parent
13ecd81fba
commit
d4ecb90b38
5 changed files with 322 additions and 1 deletions
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@ -49,7 +49,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.max_radios = 3,
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.bdf_addr = 0x4B0C0000,
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.hw_ops = &qca6390_ops,
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.ring_mask = &ath11k_hw_ring_mask_ipq8074,
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.ring_mask = &ath11k_hw_ring_mask_qca6390,
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.internal_sleep_clock = true,
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.regs = &qca6390_regs,
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.host_ce_config = ath11k_host_ce_config_qca6390,
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@ -107,6 +107,113 @@ void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring)
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ring->vaddr_unaligned = NULL;
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}
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static int ath11k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask)
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{
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int ext_group_num;
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u8 mask = 1 << ring_num;
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for (ext_group_num = 0; ext_group_num < ATH11K_EXT_IRQ_GRP_NUM_MAX;
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ext_group_num++) {
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if (mask & grp_mask[ext_group_num])
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return ext_group_num;
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}
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return -ENOENT;
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}
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static int ath11k_dp_srng_calculate_msi_group(struct ath11k_base *ab,
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enum hal_ring_type type, int ring_num)
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{
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const u8 *grp_mask;
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switch (type) {
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case HAL_WBM2SW_RELEASE:
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if (ring_num < 3) {
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grp_mask = &ab->hw_params.ring_mask->tx[0];
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} else if (ring_num == 3) {
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grp_mask = &ab->hw_params.ring_mask->rx_wbm_rel[0];
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ring_num = 0;
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} else {
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return -ENOENT;
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}
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break;
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case HAL_REO_EXCEPTION:
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grp_mask = &ab->hw_params.ring_mask->rx_err[0];
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break;
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case HAL_REO_DST:
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grp_mask = &ab->hw_params.ring_mask->rx[0];
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break;
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case HAL_REO_STATUS:
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grp_mask = &ab->hw_params.ring_mask->reo_status[0];
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break;
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case HAL_RXDMA_MONITOR_STATUS:
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case HAL_RXDMA_MONITOR_DST:
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grp_mask = &ab->hw_params.ring_mask->rx_mon_status[0];
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break;
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case HAL_RXDMA_DST:
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grp_mask = &ab->hw_params.ring_mask->rxdma2host[0];
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break;
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case HAL_RXDMA_BUF:
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grp_mask = &ab->hw_params.ring_mask->host2rxdma[0];
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break;
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case HAL_RXDMA_MONITOR_BUF:
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case HAL_TCL_DATA:
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case HAL_TCL_CMD:
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case HAL_REO_CMD:
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case HAL_SW2WBM_RELEASE:
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case HAL_WBM_IDLE_LINK:
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case HAL_TCL_STATUS:
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case HAL_REO_REINJECT:
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case HAL_CE_SRC:
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case HAL_CE_DST:
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case HAL_CE_DST_STATUS:
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default:
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return -ENOENT;
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}
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return ath11k_dp_srng_find_ring_in_mask(ring_num, grp_mask);
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}
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static void ath11k_dp_srng_msi_setup(struct ath11k_base *ab,
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struct hal_srng_params *ring_params,
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enum hal_ring_type type, int ring_num)
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{
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int msi_group_number, msi_data_count;
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u32 msi_data_start, msi_irq_start, addr_lo, addr_hi;
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int ret;
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ret = ath11k_get_user_msi_vector(ab, "DP",
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&msi_data_count, &msi_data_start,
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&msi_irq_start);
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if (ret)
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return;
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msi_group_number = ath11k_dp_srng_calculate_msi_group(ab, type,
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ring_num);
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if (msi_group_number < 0) {
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ath11k_dbg(ab, ATH11K_DBG_PCI,
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"ring not part of an ext_group; ring_type: %d,ring_num %d",
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type, ring_num);
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ring_params->msi_addr = 0;
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ring_params->msi_data = 0;
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return;
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}
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if (msi_group_number > msi_data_count) {
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ath11k_dbg(ab, ATH11K_DBG_PCI,
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"multiple msi_groups share one msi, msi_group_num %d",
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msi_group_number);
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}
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ath11k_get_msi_address(ab, &addr_lo, &addr_hi);
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ring_params->msi_addr = addr_lo;
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ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
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ring_params->msi_data = (msi_group_number % msi_data_count)
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+ msi_data_start;
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ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
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}
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int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
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enum hal_ring_type type, int ring_num,
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int mac_id, int num_entries)
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@ -136,6 +243,7 @@ int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
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params.ring_base_vaddr = ring->vaddr;
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params.ring_base_paddr = ring->paddr;
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params.num_entries = num_entries;
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ath11k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
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switch (type) {
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case HAL_REO_DST:
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@ -208,6 +208,43 @@ const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = {
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},
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};
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const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = {
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.tx = {
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ATH11K_TX_RING_MASK_0,
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ATH11K_TX_RING_MASK_1,
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ATH11K_TX_RING_MASK_2,
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},
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.rx_mon_status = {
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0, 0, 0, 0,
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ATH11K_RX_MON_STATUS_RING_MASK_0,
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ATH11K_RX_MON_STATUS_RING_MASK_1,
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ATH11K_RX_MON_STATUS_RING_MASK_2,
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},
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.rx = {
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0, 0, 0, 0, 0, 0, 0,
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ATH11K_RX_RING_MASK_0,
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ATH11K_RX_RING_MASK_1,
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ATH11K_RX_RING_MASK_2,
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ATH11K_RX_RING_MASK_3,
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},
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.rx_err = {
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ATH11K_RX_ERR_RING_MASK_0,
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},
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.rx_wbm_rel = {
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ATH11K_RX_WBM_REL_RING_MASK_0,
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},
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.reo_status = {
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ATH11K_REO_STATUS_RING_MASK_0,
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},
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.rxdma2host = {
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ATH11K_RXDMA2HOST_RING_MASK_0,
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ATH11K_RXDMA2HOST_RING_MASK_1,
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ATH11K_RXDMA2HOST_RING_MASK_2,
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},
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.host2rxdma = {
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},
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};
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const struct ath11k_hw_regs ipq8074_regs = {
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/* SW2TCL(x) R0 ring configuration address */
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.hal_tcl1_ring_base_lsb = 0x00000510,
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@ -158,6 +158,7 @@ extern const struct ath11k_hw_ops ipq6018_ops;
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extern const struct ath11k_hw_ops qca6390_ops;
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extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
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extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
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static inline
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int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
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@ -389,6 +389,20 @@ static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_nam
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base_vector);
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}
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static void ath11k_pci_free_ext_irq(struct ath11k_base *ab)
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{
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int i, j;
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for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
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struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
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for (j = 0; j < irq_grp->num_irq; j++)
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free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
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netif_napi_del(&irq_grp->napi);
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}
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}
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static void ath11k_pci_free_irq(struct ath11k_base *ab)
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{
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int i, irq_idx;
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@ -399,6 +413,8 @@ static void ath11k_pci_free_irq(struct ath11k_base *ab)
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irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
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free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
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}
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ath11k_pci_free_ext_irq(ab);
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}
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static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
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@ -461,6 +477,159 @@ static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg)
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return IRQ_HANDLED;
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}
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static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
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{
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int i;
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for (i = 0; i < irq_grp->num_irq; i++)
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disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
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}
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static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc)
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{
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int i;
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for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
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struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
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ath11k_pci_ext_grp_disable(irq_grp);
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napi_synchronize(&irq_grp->napi);
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napi_disable(&irq_grp->napi);
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}
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}
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static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
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{
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int i;
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for (i = 0; i < irq_grp->num_irq; i++)
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enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
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}
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static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
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{
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int i;
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for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
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struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
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napi_enable(&irq_grp->napi);
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ath11k_pci_ext_grp_enable(irq_grp);
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}
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}
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static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab)
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{
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int i, j, irq_idx;
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for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
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struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
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for (j = 0; j < irq_grp->num_irq; j++) {
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irq_idx = irq_grp->irqs[j];
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synchronize_irq(ab->irq_num[irq_idx]);
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}
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}
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}
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static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
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{
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__ath11k_pci_ext_irq_disable(ab);
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ath11k_pci_sync_ext_irqs(ab);
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}
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static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
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{
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struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
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struct ath11k_ext_irq_grp,
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napi);
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struct ath11k_base *ab = irq_grp->ab;
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int work_done;
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work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
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if (work_done < budget) {
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napi_complete_done(napi, work_done);
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ath11k_pci_ext_grp_enable(irq_grp);
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}
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if (work_done > budget)
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work_done = budget;
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return work_done;
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}
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static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg)
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{
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struct ath11k_ext_irq_grp *irq_grp = arg;
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ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
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ath11k_pci_ext_grp_disable(irq_grp);
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napi_schedule(&irq_grp->napi);
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return IRQ_HANDLED;
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}
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static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
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{
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int i, j, ret, num_vectors = 0;
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u32 user_base_data = 0, base_vector = 0;
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ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP",
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&num_vectors, &user_base_data,
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&base_vector);
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for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
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struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
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u32 num_irq = 0;
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irq_grp->ab = ab;
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irq_grp->grp_id = i;
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init_dummy_netdev(&irq_grp->napi_ndev);
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netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
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ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT);
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if (ab->hw_params.ring_mask->tx[i] ||
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ab->hw_params.ring_mask->rx[i] ||
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ab->hw_params.ring_mask->rx_err[i] ||
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ab->hw_params.ring_mask->rx_wbm_rel[i] ||
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ab->hw_params.ring_mask->reo_status[i] ||
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ab->hw_params.ring_mask->rxdma2host[i] ||
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ab->hw_params.ring_mask->host2rxdma[i] ||
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ab->hw_params.ring_mask->rx_mon_status[i]) {
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num_irq = 1;
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}
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irq_grp->num_irq = num_irq;
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irq_grp->irqs[0] = base_vector + i;
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for (j = 0; j < irq_grp->num_irq; j++) {
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int irq_idx = irq_grp->irqs[j];
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int vector = (i % num_vectors) + base_vector;
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int irq = ath11k_pci_get_msi_irq(ab->dev, vector);
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ab->irq_num[irq_idx] = irq;
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ath11k_dbg(ab, ATH11K_DBG_PCI,
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"irq:%d group:%d\n", irq, i);
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ret = request_irq(irq, ath11k_pci_ext_interrupt_handler,
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IRQF_SHARED,
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"DP_EXT_IRQ", irq_grp);
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if (ret) {
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ath11k_err(ab, "failed request irq %d: %d\n",
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vector, ret);
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return ret;
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}
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disable_irq_nosync(ab->irq_num[irq_idx]);
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}
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}
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return 0;
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}
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static int ath11k_pci_config_irq(struct ath11k_base *ab)
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{
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struct ath11k_ce_pipe *ce_pipe;
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@ -503,6 +672,10 @@ static int ath11k_pci_config_irq(struct ath11k_base *ab)
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ath11k_pci_ce_irq_disable(ab, i);
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}
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ret = ath11k_pci_ext_irq_config(ab);
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if (ret)
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return ret;
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return 0;
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}
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@ -757,6 +930,8 @@ static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
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.write32 = ath11k_pci_write32,
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.power_down = ath11k_pci_power_down,
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.power_up = ath11k_pci_power_up,
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.irq_enable = ath11k_pci_ext_irq_enable,
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.irq_disable = ath11k_pci_ext_irq_disable,
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.get_msi_address = ath11k_pci_get_msi_address,
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.get_user_msi_vector = ath11k_get_user_msi_assignment,
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.map_service_to_pipe = ath11k_pci_map_service_to_pipe,
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