x86/amd_nb: Move SMN access code to a new amd_node driver
SMN access was bolted into amd_nb mostly as convenience. This has limitations though that require incurring tech debt to keep it working. Move SMN access to the newly introduced AMD Node driver. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> # pdx86 Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> # PMF, PMC Link: https://lore.kernel.org/r/20241206161210.163701-11-yazen.ghannam@amd.com
This commit is contained in:
Mario Limonciello
Borislav Petkov (AMD)
parent
7dd57db495
commit
d6caeafaa3
16 changed files with 107 additions and 100 deletions
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@ -1122,6 +1122,7 @@ S: Supported
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F: drivers/i2c/busses/i2c-amd-asf-plat.c
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AMD NODE DRIVER
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M: Mario Limonciello <mario.limonciello@amd.com>
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M: Yazen Ghannam <yazen.ghannam@amd.com>
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L: linux-kernel@vger.kernel.org
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S: Supported
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@ -21,9 +21,6 @@ extern int amd_numa_init(void);
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extern int amd_get_subcaches(int);
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extern int amd_set_subcaches(int, unsigned long);
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int __must_check amd_smn_read(u16 node, u32 address, u32 *value);
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int __must_check amd_smn_write(u16 node, u32 address, u32 value);
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struct amd_l3_cache {
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unsigned indices;
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u8 subcaches[4];
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@ -30,4 +30,7 @@ static inline u16 amd_num_nodes(void)
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return topology_amd_nodes_per_pkg() * topology_max_packages();
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}
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int __must_check amd_smn_read(u16 node, u32 address, u32 *value);
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int __must_check amd_smn_write(u16 node, u32 address, u32 value);
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#endif /*_ASM_X86_AMD_NODE_H_*/
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@ -15,9 +15,6 @@
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#include <linux/pci_ids.h>
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#include <asm/amd_nb.h>
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/* Protect the PCI config register pairs used for SMN. */
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static DEFINE_MUTEX(smn_mutex);
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static u32 *flush_words;
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static const struct pci_device_id amd_nb_misc_ids[] = {
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@ -59,92 +56,6 @@ struct amd_northbridge *node_to_amd_nb(int node)
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}
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EXPORT_SYMBOL_GPL(node_to_amd_nb);
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/*
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* SMN accesses may fail in ways that are difficult to detect here in the called
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* functions amd_smn_read() and amd_smn_write(). Therefore, callers must do
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* their own checking based on what behavior they expect.
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*
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* For SMN reads, the returned value may be zero if the register is Read-as-Zero.
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* Or it may be a "PCI Error Response", e.g. all 0xFFs. The "PCI Error Response"
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* can be checked here, and a proper error code can be returned.
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*
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* But the Read-as-Zero response cannot be verified here. A value of 0 may be
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* correct in some cases, so callers must check that this correct is for the
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* register/fields they need.
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*
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* For SMN writes, success can be determined through a "write and read back"
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* However, this is not robust when done here.
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*
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* Possible issues:
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*
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* 1) Bits that are "Write-1-to-Clear". In this case, the read value should
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* *not* match the write value.
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*
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* 2) Bits that are "Read-as-Zero"/"Writes-Ignored". This information cannot be
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* known here.
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*
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* 3) Bits that are "Reserved / Set to 1". Ditto above.
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*
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* Callers of amd_smn_write() should do the "write and read back" check
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* themselves, if needed.
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*
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* For #1, they can see if their target bits got cleared.
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*
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* For #2 and #3, they can check if their target bits got set as intended.
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*
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* This matches what is done for RDMSR/WRMSR. As long as there's no #GP, then
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* the operation is considered a success, and the caller does their own
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* checking.
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*/
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static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
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{
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struct pci_dev *root;
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int err = -ENODEV;
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if (node >= amd_northbridges.num)
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goto out;
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root = node_to_amd_nb(node)->root;
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if (!root)
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goto out;
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mutex_lock(&smn_mutex);
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err = pci_write_config_dword(root, 0x60, address);
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if (err) {
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pr_warn("Error programming SMN address 0x%x.\n", address);
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goto out_unlock;
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}
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err = (write ? pci_write_config_dword(root, 0x64, *value)
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: pci_read_config_dword(root, 0x64, value));
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out_unlock:
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mutex_unlock(&smn_mutex);
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out:
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return err;
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}
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int __must_check amd_smn_read(u16 node, u32 address, u32 *value)
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{
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int err = __amd_smn_rw(node, address, value, false);
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if (PCI_POSSIBLE_ERROR(*value)) {
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err = -ENODEV;
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*value = 0;
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}
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return err;
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}
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EXPORT_SYMBOL_GPL(amd_smn_read);
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int __must_check amd_smn_write(u16 node, u32 address, u32 value)
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{
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return __amd_smn_rw(node, address, &value, true);
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}
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EXPORT_SYMBOL_GPL(amd_smn_write);
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static int amd_cache_northbridges(void)
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{
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struct amd_northbridge *nb;
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@ -8,6 +8,7 @@
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* Author: Yazen Ghannam <Yazen.Ghannam@amd.com>
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*/
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#include <asm/amd_nb.h>
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#include <asm/amd_node.h>
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/*
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@ -88,3 +89,92 @@ struct pci_dev *amd_node_get_root(u16 node)
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pci_dbg(root, "is root for AMD node %u\n", node);
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return root;
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}
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/* Protect the PCI config register pairs used for SMN. */
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static DEFINE_MUTEX(smn_mutex);
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/*
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* SMN accesses may fail in ways that are difficult to detect here in the called
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* functions amd_smn_read() and amd_smn_write(). Therefore, callers must do
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* their own checking based on what behavior they expect.
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*
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* For SMN reads, the returned value may be zero if the register is Read-as-Zero.
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* Or it may be a "PCI Error Response", e.g. all 0xFFs. The "PCI Error Response"
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* can be checked here, and a proper error code can be returned.
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*
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* But the Read-as-Zero response cannot be verified here. A value of 0 may be
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* correct in some cases, so callers must check that this correct is for the
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* register/fields they need.
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*
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* For SMN writes, success can be determined through a "write and read back"
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* However, this is not robust when done here.
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*
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* Possible issues:
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*
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* 1) Bits that are "Write-1-to-Clear". In this case, the read value should
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* *not* match the write value.
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*
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* 2) Bits that are "Read-as-Zero"/"Writes-Ignored". This information cannot be
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* known here.
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*
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* 3) Bits that are "Reserved / Set to 1". Ditto above.
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*
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* Callers of amd_smn_write() should do the "write and read back" check
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* themselves, if needed.
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*
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* For #1, they can see if their target bits got cleared.
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*
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* For #2 and #3, they can check if their target bits got set as intended.
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*
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* This matches what is done for RDMSR/WRMSR. As long as there's no #GP, then
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* the operation is considered a success, and the caller does their own
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* checking.
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*/
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static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
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{
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struct pci_dev *root;
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int err = -ENODEV;
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if (node >= amd_nb_num())
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goto out;
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root = node_to_amd_nb(node)->root;
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if (!root)
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goto out;
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mutex_lock(&smn_mutex);
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err = pci_write_config_dword(root, 0x60, address);
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if (err) {
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pr_warn("Error programming SMN address 0x%x.\n", address);
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goto out_unlock;
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}
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err = (write ? pci_write_config_dword(root, 0x64, *value)
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: pci_read_config_dword(root, 0x64, value));
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out_unlock:
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mutex_unlock(&smn_mutex);
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out:
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return err;
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}
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int __must_check amd_smn_read(u16 node, u32 address, u32 *value)
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{
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int err = __amd_smn_rw(node, address, value, false);
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if (PCI_POSSIBLE_ERROR(*value)) {
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err = -ENODEV;
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*value = 0;
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}
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return err;
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}
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EXPORT_SYMBOL_GPL(amd_smn_read);
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int __must_check amd_smn_write(u16 node, u32 address, u32 value)
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{
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return __amd_smn_rw(node, address, &value, true);
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}
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EXPORT_SYMBOL_GPL(amd_smn_write);
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@ -9,7 +9,7 @@
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#include <linux/pci.h>
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#include <linux/suspend.h>
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#include <linux/vgaarb.h>
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#include <asm/amd_nb.h>
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#include <asm/amd_node.h>
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#include <asm/hpet.h>
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#include <asm/pci_x86.h>
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@ -828,7 +828,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
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#endif
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#ifdef CONFIG_AMD_NB
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#ifdef CONFIG_AMD_NODE
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#define AMD_15B8_RCC_DEV2_EPF0_STRAP2 0x10136008
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#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L
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@ -78,6 +78,7 @@ config EDAC_GHES
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64)"
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depends on AMD_NB && EDAC_DECODE_MCE
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depends on AMD_NODE
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imply AMD_ATL
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help
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Support for error detection and correction of DRAM ECC errors on
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@ -2,6 +2,7 @@
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#include <linux/ras.h>
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#include "amd64_edac.h"
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#include <asm/amd_nb.h>
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#include <asm/amd_node.h>
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static struct edac_pci_ctl_info *pci_ctl;
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@ -324,7 +324,7 @@ config SENSORS_K8TEMP
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config SENSORS_K10TEMP
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tristate "AMD Family 10h+ temperature sensor"
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depends on X86 && PCI && AMD_NB
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depends on X86 && PCI && AMD_NODE
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help
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If you say yes here you get support for the temperature
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sensor(s) inside your CPU. Supported are later revisions of
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@ -20,7 +20,7 @@
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <asm/amd_nb.h>
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#include <asm/amd_node.h>
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#include <asm/processor.h>
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MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
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@ -5,7 +5,7 @@
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config AMD_PMC
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tristate "AMD SoC PMC driver"
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depends on ACPI && PCI && RTC_CLASS && AMD_NB
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depends on ACPI && PCI && RTC_CLASS && AMD_NODE
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depends on SUSPEND
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select SERIO
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help
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@ -10,7 +10,6 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <asm/amd_nb.h>
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#include <linux/acpi.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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@ -28,6 +27,8 @@
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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#include <asm/amd_node.h>
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#include "pmc.h"
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/* SMU communication registers */
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@ -7,7 +7,7 @@ config AMD_PMF
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tristate "AMD Platform Management Framework"
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depends on ACPI && PCI
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depends on POWER_SUPPLY
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depends on AMD_NB
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depends on AMD_NODE
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select ACPI_PLATFORM_PROFILE
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depends on TEE && AMDTEE
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depends on AMD_SFH_HID
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@ -8,13 +8,13 @@
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* Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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*/
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#include <asm/amd_nb.h>
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#include <linux/debugfs.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/power_supply.h>
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#include <asm/amd_node.h>
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#include "pmf.h"
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/* PMF-SMU communication registers */
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@ -10,6 +10,7 @@
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config AMD_ATL
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tristate "AMD Address Translation Library"
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depends on AMD_NB && X86_64 && RAS
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depends on AMD_NODE
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depends on MEMORY_FAILURE
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default N
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help
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@ -18,6 +18,7 @@
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#include <linux/ras.h>
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#include <asm/amd_nb.h>
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#include <asm/amd_node.h>
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#include "reg_fields.h"
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