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riscv: hwcap: make ISA extension ids can be used in asm

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So that ISA extensions can be used in assembly files, convert the
multi-letter RISC-V ISA extension IDs enums to macros.
In order to make them visible, move the #ifndef __ASSEMBLY__ guard
to a later point in the header

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230128172856.3814-4-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Jisheng Zhang 2023-01-29 01:28:46 +08:00 • committed by Palmer Dabbelt
parent 191b27c7c0
commit d8a3d8a752
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GPG key ID: 2E1319F35FBB1889
1 changed files with 21 additions and 24 deletions
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45
arch/riscv/include/asm/hwcap.h
View file

@ -12,20 +12,6 @@
#include <linux/bits.h> #include <linux/bits.h>
#include <uapi/asm/hwcap.h> #include <uapi/asm/hwcap.h>
#ifndef __ASSEMBLY__
#include <linux/jump_label.h>
/*
* This yields a mask that user programs can use to figure out what
* instruction set this cpu supports.
*/
#define ELF_HWCAP (elf_hwcap)
enum {
CAP_HWCAP = 1,
};
extern unsigned long elf_hwcap;
#define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_a ('a' - 'a')
#define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a')
#define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a')
@ -46,23 +32,34 @@ extern unsigned long elf_hwcap;
#define RISCV_ISA_EXT_BASE 26 #define RISCV_ISA_EXT_BASE 26
/* /*
* This enum represent the logical ID for each multi-letter RISC-V ISA extension. * These macros represent the logical ID for each multi-letter RISC-V ISA extension.
* The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
* RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
* extensions while all the multi-letter extensions should define the next * extensions while all the multi-letter extensions should define the next
* available logical extension id. * available logical extension id.
* Entries are sorted alphabetically. * Entries are sorted alphabetically.
*/ */
enum riscv_isa_ext_id { #define RISCV_ISA_EXT_SSCOFPMF 26
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, #define RISCV_ISA_EXT_SSTC 27
RISCV_ISA_EXT_SSTC, #define RISCV_ISA_EXT_SVINVAL 28
RISCV_ISA_EXT_SVINVAL, #define RISCV_ISA_EXT_SVPBMT 29
RISCV_ISA_EXT_SVPBMT, #define RISCV_ISA_EXT_ZICBOM 30
RISCV_ISA_EXT_ZICBOM, #define RISCV_ISA_EXT_ZIHINTPAUSE 31
RISCV_ISA_EXT_ZIHINTPAUSE,
RISCV_ISA_EXT_ID_MAX #ifndef __ASSEMBLY__
#include <linux/jump_label.h>
/*
* This yields a mask that user programs can use to figure out what
* instruction set this cpu supports.
*/
#define ELF_HWCAP (elf_hwcap)
enum {
CAP_HWCAP = 1,
}; };
static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);
extern unsigned long elf_hwcap;
/* /*
* This enum represents the logical ID for each RISC-V ISA extension static * This enum represents the logical ID for each RISC-V ISA extension static