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drm/nouveau: make fifo.create_context() responsible for mapping control regs

Browse source 
The regs belong to PFIFO, they're different for pretty much the same
generations we need different PFIFO control for, and NVC0 is going
to be even more different than the rest.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2010-11-22 16:05:54 +10:00 • committed by Francisco Jerez
parent 395a31ec7e
commit d908175cca
5 changed files with 29 additions and 21 deletions
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22
drivers/gpu/drm/nouveau/nouveau_channel.c
View file

@ -113,7 +113,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
struct nouveau_channel *chan; struct nouveau_channel *chan;
unsigned long flags; unsigned long flags;
int user, ret; int ret;
/* allocate and lock channel structure */ /* allocate and lock channel structure */
chan = kzalloc(sizeof(*chan), GFP_KERNEL); chan = kzalloc(sizeof(*chan), GFP_KERNEL);
@ -160,23 +160,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
} }
nouveau_dma_pre_init(chan); nouveau_dma_pre_init(chan);
/* Locate channel's user control regs */
if (dev_priv->card_type < NV_40)
user = NV03_USER(chan->id);
else
if (dev_priv->card_type < NV_50)
user = NV40_USER(chan->id);
else
user = NV50_USER(chan->id);
chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
PAGE_SIZE);
if (!chan->user) {
NV_ERROR(dev, "ioremap of regs failed.\n");
nouveau_channel_put(&chan);
return -ENOMEM;
}
chan->user_put = 0x40; chan->user_put = 0x40;
chan->user_get = 0x44; chan->user_get = 0x44;
@ -356,9 +339,6 @@ nouveau_channel_del(struct kref *ref)
struct nouveau_channel *chan = struct nouveau_channel *chan =
container_of(ref, struct nouveau_channel, ref); container_of(ref, struct nouveau_channel, ref);
if (chan->user)
iounmap(chan->user);
kfree(chan); kfree(chan);
} }

9
drivers/gpu/drm/nouveau/nv04_fifo.c
View file

@ -129,6 +129,11 @@ nv04_fifo_create_context(struct nouveau_channel *chan)
if (ret) if (ret)
return ret; return ret;
chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
NV03_USER(chan->id), PAGE_SIZE);
if (!chan->user)
return -ENOMEM;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags); spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
/* Setup initial state */ /* Setup initial state */
@ -173,6 +178,10 @@ nv04_fifo_destroy_context(struct nouveau_channel *chan)
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the channel resources */ /* Free the channel resources */
if (chan->user) {
iounmap(chan->user);
chan->user = NULL;
}
nouveau_gpuobj_ref(NULL, &chan->ramfc); nouveau_gpuobj_ref(NULL, &chan->ramfc);
} }

5
drivers/gpu/drm/nouveau/nv10_fifo.c
View file

@ -53,6 +53,11 @@ nv10_fifo_create_context(struct nouveau_channel *chan)
if (ret) if (ret)
return ret; return ret;
chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
NV03_USER(chan->id), PAGE_SIZE);
if (!chan->user)
return -ENOMEM;
/* Fill entries that are seen filled in dumps of nvidia driver just /* Fill entries that are seen filled in dumps of nvidia driver just
* after channel's is put into DMA mode * after channel's is put into DMA mode
*/ */

5
drivers/gpu/drm/nouveau/nv40_fifo.c
View file

@ -47,6 +47,11 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
if (ret) if (ret)
return ret; return ret;
chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
NV40_USER(chan->id), PAGE_SIZE);
if (!chan->user)
return -ENOMEM;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags); spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
nv_wi32(dev, fc + 0, chan->pushbuf_base); nv_wi32(dev, fc + 0, chan->pushbuf_base);

9
drivers/gpu/drm/nouveau/nv50_fifo.c
View file

@ -261,6 +261,11 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
} }
ramfc = chan->ramfc; ramfc = chan->ramfc;
chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
NV50_USER(chan->id), PAGE_SIZE);
if (!chan->user)
return -ENOMEM;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags); spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4); nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
@ -327,6 +332,10 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the channel resources */ /* Free the channel resources */
if (chan->user) {
iounmap(chan->user);
chan->user = NULL;
}
nouveau_gpuobj_ref(NULL, &ramfc); nouveau_gpuobj_ref(NULL, &ramfc);
nouveau_gpuobj_ref(NULL, &chan->cache); nouveau_gpuobj_ref(NULL, &chan->cache);
} }