RISC-V: KVM: Add in-kernel virtualization of AIA IMSIC
We can have AIA IMSIC support for both HS-level and VS-level but the VS-level IMSICs are optional. We use the VS-level IMSICs for Guest/VM whenever available otherwise we fallback to software emulation of AIA IMSIC. This patch adds in-kernel virtualization of AIA IMSIC. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
Anup Patel
parent
289a007b98
commit
db8b7e97d6
3 changed files with 925 additions and 36 deletions
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@ -90,44 +90,18 @@ DECLARE_STATIC_KEY_FALSE(kvm_riscv_aia_available);
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extern struct kvm_device_ops kvm_riscv_aia_device_ops;
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static inline void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu)
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{
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}
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static inline int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu)
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{
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return 1;
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}
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void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu);
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#define KVM_RISCV_AIA_IMSIC_TOPEI (ISELECT_MASK + 1)
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static inline int kvm_riscv_vcpu_aia_imsic_rmw(struct kvm_vcpu *vcpu,
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unsigned long isel,
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unsigned long *val,
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unsigned long new_val,
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unsigned long wr_mask)
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{
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return 0;
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}
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static inline void kvm_riscv_vcpu_aia_imsic_reset(struct kvm_vcpu *vcpu)
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{
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}
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static inline int kvm_riscv_vcpu_aia_imsic_inject(struct kvm_vcpu *vcpu,
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u32 guest_index, u32 offset,
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u32 iid)
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{
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return 0;
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}
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static inline int kvm_riscv_vcpu_aia_imsic_init(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static inline void kvm_riscv_vcpu_aia_imsic_cleanup(struct kvm_vcpu *vcpu)
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{
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}
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int kvm_riscv_vcpu_aia_imsic_rmw(struct kvm_vcpu *vcpu, unsigned long isel,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask);
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void kvm_riscv_vcpu_aia_imsic_reset(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_aia_imsic_inject(struct kvm_vcpu *vcpu,
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u32 guest_index, u32 offset, u32 iid);
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int kvm_riscv_vcpu_aia_imsic_init(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_aia_imsic_cleanup(struct kvm_vcpu *vcpu);
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int kvm_riscv_aia_aplic_set_attr(struct kvm *kvm, unsigned long type, u32 v);
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int kvm_riscv_aia_aplic_get_attr(struct kvm *kvm, unsigned long type, u32 *v);
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@ -29,3 +29,4 @@ kvm-$(CONFIG_RISCV_PMU_SBI) += vcpu_pmu.o vcpu_sbi_pmu.o
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kvm-y += aia.o
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kvm-y += aia_device.o
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kvm-y += aia_aplic.o
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kvm-y += aia_imsic.o
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914
arch/riscv/kvm/aia_imsic.c
Normal file
914
arch/riscv/kvm/aia_imsic.c
Normal file
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@ -0,0 +1,914 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#include <linux/atomic.h>
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#include <linux/bitmap.h>
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#include <linux/kvm_host.h>
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#include <linux/math.h>
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#include <linux/spinlock.h>
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#include <linux/swab.h>
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#include <kvm/iodev.h>
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#include <asm/csr.h>
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#include <asm/kvm_aia_imsic.h>
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#define IMSIC_MAX_EIX (IMSIC_MAX_ID / BITS_PER_TYPE(u64))
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struct imsic_mrif_eix {
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unsigned long eip[BITS_PER_TYPE(u64) / BITS_PER_LONG];
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unsigned long eie[BITS_PER_TYPE(u64) / BITS_PER_LONG];
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};
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struct imsic_mrif {
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struct imsic_mrif_eix eix[IMSIC_MAX_EIX];
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unsigned long eithreshold;
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unsigned long eidelivery;
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};
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struct imsic {
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struct kvm_io_device iodev;
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u32 nr_msis;
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u32 nr_eix;
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u32 nr_hw_eix;
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/*
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* At any point in time, the register state is in
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* one of the following places:
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*
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* 1) Hardware: IMSIC VS-file (vsfile_cpu >= 0)
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* 2) Software: IMSIC SW-file (vsfile_cpu < 0)
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*/
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/* IMSIC VS-file */
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rwlock_t vsfile_lock;
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int vsfile_cpu;
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int vsfile_hgei;
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void __iomem *vsfile_va;
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phys_addr_t vsfile_pa;
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/* IMSIC SW-file */
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struct imsic_mrif *swfile;
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phys_addr_t swfile_pa;
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};
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#define imsic_vs_csr_read(__c) \
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({ \
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unsigned long __r; \
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csr_write(CSR_VSISELECT, __c); \
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__r = csr_read(CSR_VSIREG); \
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__r; \
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})
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#define imsic_read_switchcase(__ireg) \
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case __ireg: \
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return imsic_vs_csr_read(__ireg);
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#define imsic_read_switchcase_2(__ireg) \
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imsic_read_switchcase(__ireg + 0) \
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imsic_read_switchcase(__ireg + 1)
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#define imsic_read_switchcase_4(__ireg) \
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imsic_read_switchcase_2(__ireg + 0) \
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imsic_read_switchcase_2(__ireg + 2)
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#define imsic_read_switchcase_8(__ireg) \
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imsic_read_switchcase_4(__ireg + 0) \
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imsic_read_switchcase_4(__ireg + 4)
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#define imsic_read_switchcase_16(__ireg) \
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imsic_read_switchcase_8(__ireg + 0) \
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imsic_read_switchcase_8(__ireg + 8)
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#define imsic_read_switchcase_32(__ireg) \
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imsic_read_switchcase_16(__ireg + 0) \
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imsic_read_switchcase_16(__ireg + 16)
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#define imsic_read_switchcase_64(__ireg) \
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imsic_read_switchcase_32(__ireg + 0) \
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imsic_read_switchcase_32(__ireg + 32)
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static unsigned long imsic_eix_read(int ireg)
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{
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switch (ireg) {
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imsic_read_switchcase_64(IMSIC_EIP0)
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imsic_read_switchcase_64(IMSIC_EIE0)
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};
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return 0;
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}
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#define imsic_vs_csr_swap(__c, __v) \
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({ \
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unsigned long __r; \
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csr_write(CSR_VSISELECT, __c); \
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__r = csr_swap(CSR_VSIREG, __v); \
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__r; \
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})
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#define imsic_swap_switchcase(__ireg, __v) \
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case __ireg: \
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return imsic_vs_csr_swap(__ireg, __v);
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#define imsic_swap_switchcase_2(__ireg, __v) \
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imsic_swap_switchcase(__ireg + 0, __v) \
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imsic_swap_switchcase(__ireg + 1, __v)
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#define imsic_swap_switchcase_4(__ireg, __v) \
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imsic_swap_switchcase_2(__ireg + 0, __v) \
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imsic_swap_switchcase_2(__ireg + 2, __v)
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#define imsic_swap_switchcase_8(__ireg, __v) \
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imsic_swap_switchcase_4(__ireg + 0, __v) \
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imsic_swap_switchcase_4(__ireg + 4, __v)
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#define imsic_swap_switchcase_16(__ireg, __v) \
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imsic_swap_switchcase_8(__ireg + 0, __v) \
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imsic_swap_switchcase_8(__ireg + 8, __v)
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#define imsic_swap_switchcase_32(__ireg, __v) \
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imsic_swap_switchcase_16(__ireg + 0, __v) \
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imsic_swap_switchcase_16(__ireg + 16, __v)
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#define imsic_swap_switchcase_64(__ireg, __v) \
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imsic_swap_switchcase_32(__ireg + 0, __v) \
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imsic_swap_switchcase_32(__ireg + 32, __v)
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static unsigned long imsic_eix_swap(int ireg, unsigned long val)
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{
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switch (ireg) {
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imsic_swap_switchcase_64(IMSIC_EIP0, val)
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imsic_swap_switchcase_64(IMSIC_EIE0, val)
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};
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return 0;
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}
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#define imsic_vs_csr_write(__c, __v) \
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do { \
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csr_write(CSR_VSISELECT, __c); \
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csr_write(CSR_VSIREG, __v); \
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} while (0)
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#define imsic_write_switchcase(__ireg, __v) \
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case __ireg: \
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imsic_vs_csr_write(__ireg, __v); \
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break;
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#define imsic_write_switchcase_2(__ireg, __v) \
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imsic_write_switchcase(__ireg + 0, __v) \
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imsic_write_switchcase(__ireg + 1, __v)
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#define imsic_write_switchcase_4(__ireg, __v) \
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imsic_write_switchcase_2(__ireg + 0, __v) \
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imsic_write_switchcase_2(__ireg + 2, __v)
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#define imsic_write_switchcase_8(__ireg, __v) \
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imsic_write_switchcase_4(__ireg + 0, __v) \
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imsic_write_switchcase_4(__ireg + 4, __v)
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#define imsic_write_switchcase_16(__ireg, __v) \
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imsic_write_switchcase_8(__ireg + 0, __v) \
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imsic_write_switchcase_8(__ireg + 8, __v)
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#define imsic_write_switchcase_32(__ireg, __v) \
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imsic_write_switchcase_16(__ireg + 0, __v) \
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imsic_write_switchcase_16(__ireg + 16, __v)
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#define imsic_write_switchcase_64(__ireg, __v) \
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imsic_write_switchcase_32(__ireg + 0, __v) \
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imsic_write_switchcase_32(__ireg + 32, __v)
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static void imsic_eix_write(int ireg, unsigned long val)
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{
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switch (ireg) {
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imsic_write_switchcase_64(IMSIC_EIP0, val)
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imsic_write_switchcase_64(IMSIC_EIE0, val)
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};
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}
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#define imsic_vs_csr_set(__c, __v) \
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do { \
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csr_write(CSR_VSISELECT, __c); \
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csr_set(CSR_VSIREG, __v); \
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} while (0)
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#define imsic_set_switchcase(__ireg, __v) \
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case __ireg: \
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imsic_vs_csr_set(__ireg, __v); \
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break;
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#define imsic_set_switchcase_2(__ireg, __v) \
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imsic_set_switchcase(__ireg + 0, __v) \
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imsic_set_switchcase(__ireg + 1, __v)
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#define imsic_set_switchcase_4(__ireg, __v) \
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imsic_set_switchcase_2(__ireg + 0, __v) \
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imsic_set_switchcase_2(__ireg + 2, __v)
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#define imsic_set_switchcase_8(__ireg, __v) \
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imsic_set_switchcase_4(__ireg + 0, __v) \
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imsic_set_switchcase_4(__ireg + 4, __v)
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#define imsic_set_switchcase_16(__ireg, __v) \
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imsic_set_switchcase_8(__ireg + 0, __v) \
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imsic_set_switchcase_8(__ireg + 8, __v)
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#define imsic_set_switchcase_32(__ireg, __v) \
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imsic_set_switchcase_16(__ireg + 0, __v) \
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imsic_set_switchcase_16(__ireg + 16, __v)
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#define imsic_set_switchcase_64(__ireg, __v) \
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imsic_set_switchcase_32(__ireg + 0, __v) \
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imsic_set_switchcase_32(__ireg + 32, __v)
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static void imsic_eix_set(int ireg, unsigned long val)
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{
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switch (ireg) {
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imsic_set_switchcase_64(IMSIC_EIP0, val)
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imsic_set_switchcase_64(IMSIC_EIE0, val)
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};
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}
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static unsigned long imsic_mrif_atomic_rmw(struct imsic_mrif *mrif,
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unsigned long *ptr,
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unsigned long new_val,
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unsigned long wr_mask)
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{
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unsigned long old_val = 0, tmp = 0;
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__asm__ __volatile__ (
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"0: lr.w.aq %1, %0\n"
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" and %2, %1, %3\n"
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" or %2, %2, %4\n"
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" sc.w.rl %2, %2, %0\n"
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" bnez %2, 0b"
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: "+A" (*ptr), "+r" (old_val), "+r" (tmp)
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: "r" (~wr_mask), "r" (new_val & wr_mask)
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: "memory");
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return old_val;
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}
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static unsigned long imsic_mrif_atomic_or(struct imsic_mrif *mrif,
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unsigned long *ptr,
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unsigned long val)
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{
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return atomic_long_fetch_or(val, (atomic_long_t *)ptr);
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}
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#define imsic_mrif_atomic_write(__mrif, __ptr, __new_val) \
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imsic_mrif_atomic_rmw(__mrif, __ptr, __new_val, -1UL)
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#define imsic_mrif_atomic_read(__mrif, __ptr) \
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imsic_mrif_atomic_or(__mrif, __ptr, 0)
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static u32 imsic_mrif_topei(struct imsic_mrif *mrif, u32 nr_eix, u32 nr_msis)
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{
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struct imsic_mrif_eix *eix;
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u32 i, imin, imax, ei, max_msi;
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unsigned long eipend[BITS_PER_TYPE(u64) / BITS_PER_LONG];
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unsigned long eithreshold = imsic_mrif_atomic_read(mrif,
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&mrif->eithreshold);
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max_msi = (eithreshold && (eithreshold <= nr_msis)) ?
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eithreshold : nr_msis;
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for (ei = 0; ei < nr_eix; ei++) {
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eix = &mrif->eix[ei];
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eipend[0] = imsic_mrif_atomic_read(mrif, &eix->eie[0]) &
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imsic_mrif_atomic_read(mrif, &eix->eip[0]);
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#ifdef CONFIG_32BIT
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eipend[1] = imsic_mrif_atomic_read(mrif, &eix->eie[1]) &
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imsic_mrif_atomic_read(mrif, &eix->eip[1]);
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if (!eipend[0] && !eipend[1])
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#else
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if (!eipend[0])
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#endif
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continue;
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imin = ei * BITS_PER_TYPE(u64);
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imax = ((imin + BITS_PER_TYPE(u64)) < max_msi) ?
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imin + BITS_PER_TYPE(u64) : max_msi;
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for (i = (!imin) ? 1 : imin; i < imax; i++) {
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if (test_bit(i - imin, eipend))
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return (i << TOPEI_ID_SHIFT) | i;
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}
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}
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return 0;
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}
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static int imsic_mrif_rmw(struct imsic_mrif *mrif, u32 nr_eix,
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unsigned long isel, unsigned long *val,
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unsigned long new_val, unsigned long wr_mask)
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{
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bool pend;
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struct imsic_mrif_eix *eix;
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unsigned long *ei, num, old_val = 0;
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switch (isel) {
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case IMSIC_EIDELIVERY:
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old_val = imsic_mrif_atomic_rmw(mrif, &mrif->eidelivery,
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new_val, wr_mask & 0x1);
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break;
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case IMSIC_EITHRESHOLD:
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old_val = imsic_mrif_atomic_rmw(mrif, &mrif->eithreshold,
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new_val, wr_mask & (IMSIC_MAX_ID - 1));
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break;
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case IMSIC_EIP0 ... IMSIC_EIP63:
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case IMSIC_EIE0 ... IMSIC_EIE63:
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if (isel >= IMSIC_EIP0 && isel <= IMSIC_EIP63) {
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pend = true;
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num = isel - IMSIC_EIP0;
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} else {
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pend = false;
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num = isel - IMSIC_EIE0;
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}
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if ((num / 2) >= nr_eix)
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return -EINVAL;
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eix = &mrif->eix[num / 2];
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#ifndef CONFIG_32BIT
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if (num & 0x1)
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return -EINVAL;
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ei = (pend) ? &eix->eip[0] : &eix->eie[0];
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#else
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ei = (pend) ? &eix->eip[num & 0x1] : &eix->eie[num & 0x1];
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#endif
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/* Bit0 of EIP0 or EIE0 is read-only */
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if (!num)
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wr_mask &= ~BIT(0);
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old_val = imsic_mrif_atomic_rmw(mrif, ei, new_val, wr_mask);
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break;
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default:
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return -ENOENT;
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};
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if (val)
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*val = old_val;
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return 0;
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}
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|
||||
struct imsic_vsfile_read_data {
|
||||
int hgei;
|
||||
u32 nr_eix;
|
||||
bool clear;
|
||||
struct imsic_mrif *mrif;
|
||||
};
|
||||
|
||||
static void imsic_vsfile_local_read(void *data)
|
||||
{
|
||||
u32 i;
|
||||
struct imsic_mrif_eix *eix;
|
||||
struct imsic_vsfile_read_data *idata = data;
|
||||
struct imsic_mrif *mrif = idata->mrif;
|
||||
unsigned long new_hstatus, old_hstatus, old_vsiselect;
|
||||
|
||||
old_vsiselect = csr_read(CSR_VSISELECT);
|
||||
old_hstatus = csr_read(CSR_HSTATUS);
|
||||
new_hstatus = old_hstatus & ~HSTATUS_VGEIN;
|
||||
new_hstatus |= ((unsigned long)idata->hgei) << HSTATUS_VGEIN_SHIFT;
|
||||
csr_write(CSR_HSTATUS, new_hstatus);
|
||||
|
||||
/*
|
||||
* We don't use imsic_mrif_atomic_xyz() functions to store
|
||||
* values in MRIF because imsic_vsfile_read() is always called
|
||||
* with pointer to temporary MRIF on stack.
|
||||
*/
|
||||
|
||||
if (idata->clear) {
|
||||
mrif->eidelivery = imsic_vs_csr_swap(IMSIC_EIDELIVERY, 0);
|
||||
mrif->eithreshold = imsic_vs_csr_swap(IMSIC_EITHRESHOLD, 0);
|
||||
for (i = 0; i < idata->nr_eix; i++) {
|
||||
eix = &mrif->eix[i];
|
||||
eix->eip[0] = imsic_eix_swap(IMSIC_EIP0 + i * 2, 0);
|
||||
eix->eie[0] = imsic_eix_swap(IMSIC_EIE0 + i * 2, 0);
|
||||
#ifdef CONFIG_32BIT
|
||||
eix->eip[1] = imsic_eix_swap(IMSIC_EIP0 + i * 2 + 1, 0);
|
||||
eix->eie[1] = imsic_eix_swap(IMSIC_EIE0 + i * 2 + 1, 0);
|
||||
#endif
|
||||
}
|
||||
} else {
|
||||
mrif->eidelivery = imsic_vs_csr_read(IMSIC_EIDELIVERY);
|
||||
mrif->eithreshold = imsic_vs_csr_read(IMSIC_EITHRESHOLD);
|
||||
for (i = 0; i < idata->nr_eix; i++) {
|
||||
eix = &mrif->eix[i];
|
||||
eix->eip[0] = imsic_eix_read(IMSIC_EIP0 + i * 2);
|
||||
eix->eie[0] = imsic_eix_read(IMSIC_EIE0 + i * 2);
|
||||
#ifdef CONFIG_32BIT
|
||||
eix->eip[1] = imsic_eix_read(IMSIC_EIP0 + i * 2 + 1);
|
||||
eix->eie[1] = imsic_eix_read(IMSIC_EIE0 + i * 2 + 1);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
csr_write(CSR_HSTATUS, old_hstatus);
|
||||
csr_write(CSR_VSISELECT, old_vsiselect);
|
||||
}
|
||||
|
||||
static void imsic_vsfile_read(int vsfile_hgei, int vsfile_cpu, u32 nr_eix,
|
||||
bool clear, struct imsic_mrif *mrif)
|
||||
{
|
||||
struct imsic_vsfile_read_data idata;
|
||||
|
||||
/* We can only read clear if we have a IMSIC VS-file */
|
||||
if (vsfile_cpu < 0 || vsfile_hgei <= 0)
|
||||
return;
|
||||
|
||||
/* We can only read clear on local CPU */
|
||||
idata.hgei = vsfile_hgei;
|
||||
idata.nr_eix = nr_eix;
|
||||
idata.clear = clear;
|
||||
idata.mrif = mrif;
|
||||
on_each_cpu_mask(cpumask_of(vsfile_cpu),
|
||||
imsic_vsfile_local_read, &idata, 1);
|
||||
}
|
||||
|
||||
static void imsic_vsfile_local_clear(int vsfile_hgei, u32 nr_eix)
|
||||
{
|
||||
u32 i;
|
||||
unsigned long new_hstatus, old_hstatus, old_vsiselect;
|
||||
|
||||
/* We can only zero-out if we have a IMSIC VS-file */
|
||||
if (vsfile_hgei <= 0)
|
||||
return;
|
||||
|
||||
old_vsiselect = csr_read(CSR_VSISELECT);
|
||||
old_hstatus = csr_read(CSR_HSTATUS);
|
||||
new_hstatus = old_hstatus & ~HSTATUS_VGEIN;
|
||||
new_hstatus |= ((unsigned long)vsfile_hgei) << HSTATUS_VGEIN_SHIFT;
|
||||
csr_write(CSR_HSTATUS, new_hstatus);
|
||||
|
||||
imsic_vs_csr_write(IMSIC_EIDELIVERY, 0);
|
||||
imsic_vs_csr_write(IMSIC_EITHRESHOLD, 0);
|
||||
for (i = 0; i < nr_eix; i++) {
|
||||
imsic_eix_write(IMSIC_EIP0 + i * 2, 0);
|
||||
imsic_eix_write(IMSIC_EIE0 + i * 2, 0);
|
||||
#ifdef CONFIG_32BIT
|
||||
imsic_eix_write(IMSIC_EIP0 + i * 2 + 1, 0);
|
||||
imsic_eix_write(IMSIC_EIE0 + i * 2 + 1, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
csr_write(CSR_HSTATUS, old_hstatus);
|
||||
csr_write(CSR_VSISELECT, old_vsiselect);
|
||||
}
|
||||
|
||||
static void imsic_vsfile_local_update(int vsfile_hgei, u32 nr_eix,
|
||||
struct imsic_mrif *mrif)
|
||||
{
|
||||
u32 i;
|
||||
struct imsic_mrif_eix *eix;
|
||||
unsigned long new_hstatus, old_hstatus, old_vsiselect;
|
||||
|
||||
/* We can only update if we have a HW IMSIC context */
|
||||
if (vsfile_hgei <= 0)
|
||||
return;
|
||||
|
||||
/*
|
||||
* We don't use imsic_mrif_atomic_xyz() functions to read values
|
||||
* from MRIF in this function because it is always called with
|
||||
* pointer to temporary MRIF on stack.
|
||||
*/
|
||||
|
||||
old_vsiselect = csr_read(CSR_VSISELECT);
|
||||
old_hstatus = csr_read(CSR_HSTATUS);
|
||||
new_hstatus = old_hstatus & ~HSTATUS_VGEIN;
|
||||
new_hstatus |= ((unsigned long)vsfile_hgei) << HSTATUS_VGEIN_SHIFT;
|
||||
csr_write(CSR_HSTATUS, new_hstatus);
|
||||
|
||||
for (i = 0; i < nr_eix; i++) {
|
||||
eix = &mrif->eix[i];
|
||||
imsic_eix_set(IMSIC_EIP0 + i * 2, eix->eip[0]);
|
||||
imsic_eix_set(IMSIC_EIE0 + i * 2, eix->eie[0]);
|
||||
#ifdef CONFIG_32BIT
|
||||
imsic_eix_set(IMSIC_EIP0 + i * 2 + 1, eix->eip[1]);
|
||||
imsic_eix_set(IMSIC_EIE0 + i * 2 + 1, eix->eie[1]);
|
||||
#endif
|
||||
}
|
||||
imsic_vs_csr_write(IMSIC_EITHRESHOLD, mrif->eithreshold);
|
||||
imsic_vs_csr_write(IMSIC_EIDELIVERY, mrif->eidelivery);
|
||||
|
||||
csr_write(CSR_HSTATUS, old_hstatus);
|
||||
csr_write(CSR_VSISELECT, old_vsiselect);
|
||||
}
|
||||
|
||||
static void imsic_vsfile_cleanup(struct imsic *imsic)
|
||||
{
|
||||
int old_vsfile_hgei, old_vsfile_cpu;
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* We don't use imsic_mrif_atomic_xyz() functions to clear the
|
||||
* SW-file in this function because it is always called when the
|
||||
* VCPU is being destroyed.
|
||||
*/
|
||||
|
||||
write_lock_irqsave(&imsic->vsfile_lock, flags);
|
||||
old_vsfile_hgei = imsic->vsfile_hgei;
|
||||
old_vsfile_cpu = imsic->vsfile_cpu;
|
||||
imsic->vsfile_cpu = imsic->vsfile_hgei = -1;
|
||||
imsic->vsfile_va = NULL;
|
||||
imsic->vsfile_pa = 0;
|
||||
write_unlock_irqrestore(&imsic->vsfile_lock, flags);
|
||||
|
||||
memset(imsic->swfile, 0, sizeof(*imsic->swfile));
|
||||
|
||||
if (old_vsfile_cpu >= 0)
|
||||
kvm_riscv_aia_free_hgei(old_vsfile_cpu, old_vsfile_hgei);
|
||||
}
|
||||
|
||||
static void imsic_swfile_extirq_update(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
struct imsic_mrif *mrif = imsic->swfile;
|
||||
|
||||
if (imsic_mrif_atomic_read(mrif, &mrif->eidelivery) &&
|
||||
imsic_mrif_topei(mrif, imsic->nr_eix, imsic->nr_msis))
|
||||
kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT);
|
||||
else
|
||||
kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT);
|
||||
}
|
||||
|
||||
static void imsic_swfile_read(struct kvm_vcpu *vcpu, bool clear,
|
||||
struct imsic_mrif *mrif)
|
||||
{
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
|
||||
/*
|
||||
* We don't use imsic_mrif_atomic_xyz() functions to read and
|
||||
* write SW-file and MRIF in this function because it is always
|
||||
* called when VCPU is not using SW-file and the MRIF points to
|
||||
* a temporary MRIF on stack.
|
||||
*/
|
||||
|
||||
memcpy(mrif, imsic->swfile, sizeof(*mrif));
|
||||
if (clear) {
|
||||
memset(imsic->swfile, 0, sizeof(*imsic->swfile));
|
||||
kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT);
|
||||
}
|
||||
}
|
||||
|
||||
static void imsic_swfile_update(struct kvm_vcpu *vcpu,
|
||||
struct imsic_mrif *mrif)
|
||||
{
|
||||
u32 i;
|
||||
struct imsic_mrif_eix *seix, *eix;
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
struct imsic_mrif *smrif = imsic->swfile;
|
||||
|
||||
imsic_mrif_atomic_write(smrif, &smrif->eidelivery, mrif->eidelivery);
|
||||
imsic_mrif_atomic_write(smrif, &smrif->eithreshold, mrif->eithreshold);
|
||||
for (i = 0; i < imsic->nr_eix; i++) {
|
||||
seix = &smrif->eix[i];
|
||||
eix = &mrif->eix[i];
|
||||
imsic_mrif_atomic_or(smrif, &seix->eip[0], eix->eip[0]);
|
||||
imsic_mrif_atomic_or(smrif, &seix->eie[0], eix->eie[0]);
|
||||
#ifdef CONFIG_32BIT
|
||||
imsic_mrif_atomic_or(smrif, &seix->eip[1], eix->eip[1]);
|
||||
imsic_mrif_atomic_or(smrif, &seix->eie[1], eix->eie[1]);
|
||||
#endif
|
||||
}
|
||||
|
||||
imsic_swfile_extirq_update(vcpu);
|
||||
}
|
||||
|
||||
void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct imsic_mrif tmrif;
|
||||
int old_vsfile_hgei, old_vsfile_cpu;
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
|
||||
/* Read and clear IMSIC VS-file details */
|
||||
write_lock_irqsave(&imsic->vsfile_lock, flags);
|
||||
old_vsfile_hgei = imsic->vsfile_hgei;
|
||||
old_vsfile_cpu = imsic->vsfile_cpu;
|
||||
imsic->vsfile_cpu = imsic->vsfile_hgei = -1;
|
||||
imsic->vsfile_va = NULL;
|
||||
imsic->vsfile_pa = 0;
|
||||
write_unlock_irqrestore(&imsic->vsfile_lock, flags);
|
||||
|
||||
/* Do nothing, if no IMSIC VS-file to release */
|
||||
if (old_vsfile_cpu < 0)
|
||||
return;
|
||||
|
||||
/*
|
||||
* At this point, all interrupt producers are still using
|
||||
* the old IMSIC VS-file so we first re-direct all interrupt
|
||||
* producers.
|
||||
*/
|
||||
|
||||
/* Purge the G-stage mapping */
|
||||
kvm_riscv_gstage_iounmap(vcpu->kvm,
|
||||
vcpu->arch.aia_context.imsic_addr,
|
||||
IMSIC_MMIO_PAGE_SZ);
|
||||
|
||||
/* TODO: Purge the IOMMU mapping ??? */
|
||||
|
||||
/*
|
||||
* At this point, all interrupt producers have been re-directed
|
||||
* to somewhere else so we move register state from the old IMSIC
|
||||
* VS-file to the IMSIC SW-file.
|
||||
*/
|
||||
|
||||
/* Read and clear register state from old IMSIC VS-file */
|
||||
memset(&tmrif, 0, sizeof(tmrif));
|
||||
imsic_vsfile_read(old_vsfile_hgei, old_vsfile_cpu, imsic->nr_hw_eix,
|
||||
true, &tmrif);
|
||||
|
||||
/* Update register state in IMSIC SW-file */
|
||||
imsic_swfile_update(vcpu, &tmrif);
|
||||
|
||||
/* Free-up old IMSIC VS-file */
|
||||
kvm_riscv_aia_free_hgei(old_vsfile_cpu, old_vsfile_hgei);
|
||||
}
|
||||
|
||||
int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
unsigned long flags;
|
||||
phys_addr_t new_vsfile_pa;
|
||||
struct imsic_mrif tmrif;
|
||||
void __iomem *new_vsfile_va;
|
||||
struct kvm *kvm = vcpu->kvm;
|
||||
struct kvm_run *run = vcpu->run;
|
||||
struct kvm_vcpu_aia *vaia = &vcpu->arch.aia_context;
|
||||
struct imsic *imsic = vaia->imsic_state;
|
||||
int ret = 0, new_vsfile_hgei = -1, old_vsfile_hgei, old_vsfile_cpu;
|
||||
|
||||
/* Do nothing for emulation mode */
|
||||
if (kvm->arch.aia.mode == KVM_DEV_RISCV_AIA_MODE_EMUL)
|
||||
return 1;
|
||||
|
||||
/* Read old IMSIC VS-file details */
|
||||
read_lock_irqsave(&imsic->vsfile_lock, flags);
|
||||
old_vsfile_hgei = imsic->vsfile_hgei;
|
||||
old_vsfile_cpu = imsic->vsfile_cpu;
|
||||
read_unlock_irqrestore(&imsic->vsfile_lock, flags);
|
||||
|
||||
/* Do nothing if we are continuing on same CPU */
|
||||
if (old_vsfile_cpu == vcpu->cpu)
|
||||
return 1;
|
||||
|
||||
/* Allocate new IMSIC VS-file */
|
||||
ret = kvm_riscv_aia_alloc_hgei(vcpu->cpu, vcpu,
|
||||
&new_vsfile_va, &new_vsfile_pa);
|
||||
if (ret <= 0) {
|
||||
/* For HW acceleration mode, we can't continue */
|
||||
if (kvm->arch.aia.mode == KVM_DEV_RISCV_AIA_MODE_HWACCEL) {
|
||||
run->fail_entry.hardware_entry_failure_reason =
|
||||
CSR_HSTATUS;
|
||||
run->fail_entry.cpu = vcpu->cpu;
|
||||
run->exit_reason = KVM_EXIT_FAIL_ENTRY;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Release old IMSIC VS-file */
|
||||
if (old_vsfile_cpu >= 0)
|
||||
kvm_riscv_vcpu_aia_imsic_release(vcpu);
|
||||
|
||||
/* For automatic mode, we continue */
|
||||
goto done;
|
||||
}
|
||||
new_vsfile_hgei = ret;
|
||||
|
||||
/*
|
||||
* At this point, all interrupt producers are still using
|
||||
* to the old IMSIC VS-file so we first move all interrupt
|
||||
* producers to the new IMSIC VS-file.
|
||||
*/
|
||||
|
||||
/* Zero-out new IMSIC VS-file */
|
||||
imsic_vsfile_local_clear(new_vsfile_hgei, imsic->nr_hw_eix);
|
||||
|
||||
/* Update G-stage mapping for the new IMSIC VS-file */
|
||||
ret = kvm_riscv_gstage_ioremap(kvm, vcpu->arch.aia_context.imsic_addr,
|
||||
new_vsfile_pa, IMSIC_MMIO_PAGE_SZ,
|
||||
true, true);
|
||||
if (ret)
|
||||
goto fail_free_vsfile_hgei;
|
||||
|
||||
/* TODO: Update the IOMMU mapping ??? */
|
||||
|
||||
/* Update new IMSIC VS-file details in IMSIC context */
|
||||
write_lock_irqsave(&imsic->vsfile_lock, flags);
|
||||
imsic->vsfile_hgei = new_vsfile_hgei;
|
||||
imsic->vsfile_cpu = vcpu->cpu;
|
||||
imsic->vsfile_va = new_vsfile_va;
|
||||
imsic->vsfile_pa = new_vsfile_pa;
|
||||
write_unlock_irqrestore(&imsic->vsfile_lock, flags);
|
||||
|
||||
/*
|
||||
* At this point, all interrupt producers have been moved
|
||||
* to the new IMSIC VS-file so we move register state from
|
||||
* the old IMSIC VS/SW-file to the new IMSIC VS-file.
|
||||
*/
|
||||
|
||||
memset(&tmrif, 0, sizeof(tmrif));
|
||||
if (old_vsfile_cpu >= 0) {
|
||||
/* Read and clear register state from old IMSIC VS-file */
|
||||
imsic_vsfile_read(old_vsfile_hgei, old_vsfile_cpu,
|
||||
imsic->nr_hw_eix, true, &tmrif);
|
||||
|
||||
/* Free-up old IMSIC VS-file */
|
||||
kvm_riscv_aia_free_hgei(old_vsfile_cpu, old_vsfile_hgei);
|
||||
} else {
|
||||
/* Read and clear register state from IMSIC SW-file */
|
||||
imsic_swfile_read(vcpu, true, &tmrif);
|
||||
}
|
||||
|
||||
/* Restore register state in the new IMSIC VS-file */
|
||||
imsic_vsfile_local_update(new_vsfile_hgei, imsic->nr_hw_eix, &tmrif);
|
||||
|
||||
done:
|
||||
/* Set VCPU HSTATUS.VGEIN to new IMSIC VS-file */
|
||||
vcpu->arch.guest_context.hstatus &= ~HSTATUS_VGEIN;
|
||||
if (new_vsfile_hgei > 0)
|
||||
vcpu->arch.guest_context.hstatus |=
|
||||
((unsigned long)new_vsfile_hgei) << HSTATUS_VGEIN_SHIFT;
|
||||
|
||||
/* Continue run-loop */
|
||||
return 1;
|
||||
|
||||
fail_free_vsfile_hgei:
|
||||
kvm_riscv_aia_free_hgei(vcpu->cpu, new_vsfile_hgei);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int kvm_riscv_vcpu_aia_imsic_rmw(struct kvm_vcpu *vcpu, unsigned long isel,
|
||||
unsigned long *val, unsigned long new_val,
|
||||
unsigned long wr_mask)
|
||||
{
|
||||
u32 topei;
|
||||
struct imsic_mrif_eix *eix;
|
||||
int r, rc = KVM_INSN_CONTINUE_NEXT_SEPC;
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
|
||||
if (isel == KVM_RISCV_AIA_IMSIC_TOPEI) {
|
||||
/* Read pending and enabled interrupt with highest priority */
|
||||
topei = imsic_mrif_topei(imsic->swfile, imsic->nr_eix,
|
||||
imsic->nr_msis);
|
||||
if (val)
|
||||
*val = topei;
|
||||
|
||||
/* Writes ignore value and clear top pending interrupt */
|
||||
if (topei && wr_mask) {
|
||||
topei >>= TOPEI_ID_SHIFT;
|
||||
if (topei) {
|
||||
eix = &imsic->swfile->eix[topei /
|
||||
BITS_PER_TYPE(u64)];
|
||||
clear_bit(topei & (BITS_PER_TYPE(u64) - 1),
|
||||
eix->eip);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
r = imsic_mrif_rmw(imsic->swfile, imsic->nr_eix, isel,
|
||||
val, new_val, wr_mask);
|
||||
/* Forward unknown IMSIC register to user-space */
|
||||
if (r)
|
||||
rc = (r == -ENOENT) ? 0 : KVM_INSN_ILLEGAL_TRAP;
|
||||
}
|
||||
|
||||
if (wr_mask)
|
||||
imsic_swfile_extirq_update(vcpu);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
void kvm_riscv_vcpu_aia_imsic_reset(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
|
||||
if (!imsic)
|
||||
return;
|
||||
|
||||
kvm_riscv_vcpu_aia_imsic_release(vcpu);
|
||||
|
||||
memset(imsic->swfile, 0, sizeof(*imsic->swfile));
|
||||
}
|
||||
|
||||
int kvm_riscv_vcpu_aia_imsic_inject(struct kvm_vcpu *vcpu,
|
||||
u32 guest_index, u32 offset, u32 iid)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct imsic_mrif_eix *eix;
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
|
||||
/* We only emulate one IMSIC MMIO page for each Guest VCPU */
|
||||
if (!imsic || !iid || guest_index ||
|
||||
(offset != IMSIC_MMIO_SETIPNUM_LE &&
|
||||
offset != IMSIC_MMIO_SETIPNUM_BE))
|
||||
return -ENODEV;
|
||||
|
||||
iid = (offset == IMSIC_MMIO_SETIPNUM_BE) ? __swab32(iid) : iid;
|
||||
if (imsic->nr_msis <= iid)
|
||||
return -EINVAL;
|
||||
|
||||
read_lock_irqsave(&imsic->vsfile_lock, flags);
|
||||
|
||||
if (imsic->vsfile_cpu >= 0) {
|
||||
writel(iid, imsic->vsfile_va + IMSIC_MMIO_SETIPNUM_LE);
|
||||
kvm_vcpu_kick(vcpu);
|
||||
} else {
|
||||
eix = &imsic->swfile->eix[iid / BITS_PER_TYPE(u64)];
|
||||
set_bit(iid & (BITS_PER_TYPE(u64) - 1), eix->eip);
|
||||
imsic_swfile_extirq_update(vcpu);
|
||||
}
|
||||
|
||||
read_unlock_irqrestore(&imsic->vsfile_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imsic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, void *val)
|
||||
{
|
||||
if (len != 4 || (addr & 0x3) != 0)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
*((u32 *)val) = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imsic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
struct kvm_msi msi = { 0 };
|
||||
|
||||
if (len != 4 || (addr & 0x3) != 0)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
msi.address_hi = addr >> 32;
|
||||
msi.address_lo = (u32)addr;
|
||||
msi.data = *((const u32 *)val);
|
||||
kvm_riscv_aia_inject_msi(vcpu->kvm, &msi);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
static struct kvm_io_device_ops imsic_iodoev_ops = {
|
||||
.read = imsic_mmio_read,
|
||||
.write = imsic_mmio_write,
|
||||
};
|
||||
|
||||
int kvm_riscv_vcpu_aia_imsic_init(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
int ret = 0;
|
||||
struct imsic *imsic;
|
||||
struct page *swfile_page;
|
||||
struct kvm *kvm = vcpu->kvm;
|
||||
|
||||
/* Fail if we have zero IDs */
|
||||
if (!kvm->arch.aia.nr_ids)
|
||||
return -EINVAL;
|
||||
|
||||
/* Allocate IMSIC context */
|
||||
imsic = kzalloc(sizeof(*imsic), GFP_KERNEL);
|
||||
if (!imsic)
|
||||
return -ENOMEM;
|
||||
vcpu->arch.aia_context.imsic_state = imsic;
|
||||
|
||||
/* Setup IMSIC context */
|
||||
imsic->nr_msis = kvm->arch.aia.nr_ids + 1;
|
||||
rwlock_init(&imsic->vsfile_lock);
|
||||
imsic->nr_eix = BITS_TO_U64(imsic->nr_msis);
|
||||
imsic->nr_hw_eix = BITS_TO_U64(kvm_riscv_aia_max_ids);
|
||||
imsic->vsfile_hgei = imsic->vsfile_cpu = -1;
|
||||
|
||||
/* Setup IMSIC SW-file */
|
||||
swfile_page = alloc_pages(GFP_KERNEL | __GFP_ZERO,
|
||||
get_order(sizeof(*imsic->swfile)));
|
||||
if (!swfile_page) {
|
||||
ret = -ENOMEM;
|
||||
goto fail_free_imsic;
|
||||
}
|
||||
imsic->swfile = page_to_virt(swfile_page);
|
||||
imsic->swfile_pa = page_to_phys(swfile_page);
|
||||
|
||||
/* Setup IO device */
|
||||
kvm_iodevice_init(&imsic->iodev, &imsic_iodoev_ops);
|
||||
mutex_lock(&kvm->slots_lock);
|
||||
ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS,
|
||||
vcpu->arch.aia_context.imsic_addr,
|
||||
KVM_DEV_RISCV_IMSIC_SIZE,
|
||||
&imsic->iodev);
|
||||
mutex_unlock(&kvm->slots_lock);
|
||||
if (ret)
|
||||
goto fail_free_swfile;
|
||||
|
||||
return 0;
|
||||
|
||||
fail_free_swfile:
|
||||
free_pages((unsigned long)imsic->swfile,
|
||||
get_order(sizeof(*imsic->swfile)));
|
||||
fail_free_imsic:
|
||||
vcpu->arch.aia_context.imsic_state = NULL;
|
||||
kfree(imsic);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void kvm_riscv_vcpu_aia_imsic_cleanup(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct kvm *kvm = vcpu->kvm;
|
||||
struct imsic *imsic = vcpu->arch.aia_context.imsic_state;
|
||||
|
||||
if (!imsic)
|
||||
return;
|
||||
|
||||
imsic_vsfile_cleanup(imsic);
|
||||
|
||||
mutex_lock(&kvm->slots_lock);
|
||||
kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &imsic->iodev);
|
||||
mutex_unlock(&kvm->slots_lock);
|
||||
|
||||
free_pages((unsigned long)imsic->swfile,
|
||||
get_order(sizeof(*imsic->swfile)));
|
||||
|
||||
vcpu->arch.aia_context.imsic_state = NULL;
|
||||
kfree(imsic);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue