drm/i915/gvt: optimize for vGPU mmio switch
Now mmio switch between vGPUs need to switch to host first then to expected vGPU, it waste one time mmio save/restore. r/w mmio usually is time-consuming, and there are so many mocs registers need to save/restore during vGPU switch. Combine the switch_to_host and switch_to_vgpu can reduce 1 time mmio save/restore, it will reduce the CPU utilization and performance while there is multi VMs with heavy work load. Signed-off-by: Weinan Li <weinan.z.li@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Weinan Li
Zhenyu Wang
parent
dc5718f47c
commit
e47107ad37
1 changed files with 85 additions and 111 deletions
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@ -198,9 +198,10 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
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gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
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}
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static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
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static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
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int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct drm_i915_private *dev_priv;
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i915_reg_t offset, l3_offset;
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u32 regs[] = {
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[RCS] = 0xc800,
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@ -211,54 +212,44 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
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};
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int i;
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dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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offset.reg = regs[ring_id];
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for (i = 0; i < 64; i++) {
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gen9_render_mocs[ring_id][i] = I915_READ_FW(offset);
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I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset));
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if (pre)
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vgpu_vreg(pre, offset) =
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I915_READ_FW(offset);
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else
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gen9_render_mocs[ring_id][i] =
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I915_READ_FW(offset);
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if (next)
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I915_WRITE_FW(offset, vgpu_vreg(next, offset));
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else
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I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
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offset.reg += 4;
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}
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if (ring_id == RCS) {
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l3_offset.reg = 0xb020;
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for (i = 0; i < 32; i++) {
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gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset);
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I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset));
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l3_offset.reg += 4;
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}
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}
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}
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if (pre)
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vgpu_vreg(pre, l3_offset) =
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I915_READ_FW(l3_offset);
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else
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gen9_render_mocs_L3[i] =
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I915_READ_FW(l3_offset);
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if (next)
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I915_WRITE_FW(l3_offset,
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vgpu_vreg(next, l3_offset));
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else
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I915_WRITE_FW(l3_offset,
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gen9_render_mocs_L3[i]);
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static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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i915_reg_t offset, l3_offset;
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u32 regs[] = {
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[RCS] = 0xc800,
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[VCS] = 0xc900,
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[VCS2] = 0xca00,
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[BCS] = 0xcc00,
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[VECS] = 0xcb00,
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};
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int i;
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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offset.reg = regs[ring_id];
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for (i = 0; i < 64; i++) {
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vgpu_vreg(vgpu, offset) = I915_READ_FW(offset);
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I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
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offset.reg += 4;
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}
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if (ring_id == RCS) {
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l3_offset.reg = 0xb020;
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for (i = 0; i < 32; i++) {
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vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset);
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I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]);
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l3_offset.reg += 4;
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}
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}
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@ -266,84 +257,77 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
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#define CTX_CONTEXT_CONTROL_VAL 0x03
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/* Switch ring mmio values (context) from host to a vgpu. */
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static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
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/* Switch ring mmio values (context). */
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static void switch_mmio(struct intel_vgpu *pre,
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struct intel_vgpu *next,
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int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct intel_vgpu_submission *s = &vgpu->submission;
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u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state;
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u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
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struct drm_i915_private *dev_priv;
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struct intel_vgpu_submission *s;
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u32 *reg_state, ctx_ctrl;
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u32 inhibit_mask =
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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struct engine_mmio *mmio;
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u32 v;
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u32 old_v, new_v;
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dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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load_mocs(vgpu, ring_id);
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switch_mocs(pre, next, ring_id);
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mmio = vgpu->gvt->engine_mmio_list;
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mmio = dev_priv->gvt->engine_mmio_list;
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while (i915_mmio_reg_offset((mmio++)->reg)) {
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if (mmio->ring_id != ring_id)
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continue;
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mmio->value = I915_READ_FW(mmio->reg);
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/*
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* if it is an inhibit context, load in_context mmio
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* into HW by mmio write. If it is not, skip this mmio
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* write.
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*/
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if (mmio->in_context &&
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(ctx_ctrl & inhibit_mask) != inhibit_mask)
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continue;
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if (mmio->mask)
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v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
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else
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v = vgpu_vreg(vgpu, mmio->reg);
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I915_WRITE_FW(mmio->reg, v);
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trace_render_mmio(0, vgpu->id, "switch",
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i915_mmio_reg_offset(mmio->reg),
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mmio->value, v);
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}
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handle_tlb_pending_event(vgpu, ring_id);
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}
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/* Switch ring mmio values (context) from vgpu to host. */
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static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct engine_mmio *mmio;
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u32 v;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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restore_mocs(vgpu, ring_id);
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mmio = vgpu->gvt->engine_mmio_list;
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while (i915_mmio_reg_offset((mmio++)->reg)) {
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if (mmio->ring_id != ring_id)
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continue;
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vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg);
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if (mmio->mask) {
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vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16);
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v = mmio->value | (mmio->mask << 16);
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// save
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if (pre) {
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vgpu_vreg(pre, mmio->reg) = I915_READ_FW(mmio->reg);
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if (mmio->mask)
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vgpu_vreg(pre, mmio->reg) &=
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~(mmio->mask << 16);
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old_v = vgpu_vreg(pre, mmio->reg);
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} else
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v = mmio->value;
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old_v = mmio->value = I915_READ_FW(mmio->reg);
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if (mmio->in_context)
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continue;
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// restore
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if (next) {
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s = &next->submission;
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reg_state =
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s->shadow_ctx->engine[ring_id].lrc_reg_state;
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ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
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/*
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* if it is an inhibit context, load in_context mmio
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* into HW by mmio write. If it is not, skip this mmio
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* write.
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*/
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if (mmio->in_context &&
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(ctx_ctrl & inhibit_mask) != inhibit_mask)
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continue;
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I915_WRITE_FW(mmio->reg, v);
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if (mmio->mask)
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new_v = vgpu_vreg(next, mmio->reg) |
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(mmio->mask << 16);
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else
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new_v = vgpu_vreg(next, mmio->reg);
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} else {
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if (mmio->in_context)
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continue;
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if (mmio->mask)
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new_v = mmio->value | (mmio->mask << 16);
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else
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new_v = mmio->value;
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}
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trace_render_mmio(vgpu->id, 0, "switch",
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I915_WRITE_FW(mmio->reg, new_v);
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trace_render_mmio(pre ? pre->id : 0,
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next ? next->id : 0,
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"switch",
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i915_mmio_reg_offset(mmio->reg),
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mmio->value, v);
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old_v, new_v);
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}
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if (next)
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handle_tlb_pending_event(next, ring_id);
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}
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/**
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@ -374,17 +358,7 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
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* handle forcewake mannually.
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*/
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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/**
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* TODO: Optimize for vGPU to vGPU switch by merging
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* switch_mmio_to_host() and switch_mmio_to_vgpu().
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*/
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if (pre)
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switch_mmio_to_host(pre, ring_id);
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if (next)
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switch_mmio_to_vgpu(next, ring_id);
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switch_mmio(pre, next, ring_id);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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}
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