ARM: dts: qcom: sdx55: Add support for PCIe EP
Add support for PCIe Endpoint controller on the Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211126070520.28979-4-manivannan.sadhasivam@linaro.org
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@ -8,6 +8,7 @@
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#include <dt-bindings/clock/qcom,gcc-sdx55.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,sdx55.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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@ -391,6 +392,11 @@
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#hwlock-cells = <1>;
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};
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tcsr: syscon@1fcb000 {
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compatible = "syscon";
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reg = <0x01fc0000 0x1000>;
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};
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sdhc_1: sdhci@8804000 {
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compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x08804000 0x1000>;
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@ -403,6 +409,45 @@
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status = "disabled";
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};
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pcie_ep: pcie-ep@40000000 {
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compatible = "qcom,sdx55-pcie-ep";
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reg = <0x01c00000 0x3000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xc8>,
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<0x40001000 0x1000>,
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<0x40002000 0x10000>,
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<0x01c03000 0x3000>;
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reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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"mmio";
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qcom,perst-regs = <&tcsr 0xb258 0xb270>;
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clocks = <&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>;
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clock-names = "aux", "cfg", "bus_master", "bus_slave",
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"slave_q2a", "sleep", "ref";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global", "doorbell";
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reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_PCIE_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE_GDSC>;
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phys = <&pcie0_lane>;
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phy-names = "pciephy";
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max-link-speed = <3>;
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num-lanes = <2>;
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status = "disabled";
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};
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remoteproc_mpss: remoteproc@4080000 {
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compatible = "qcom,sdx55-mpss-pas";
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reg = <0x04080000 0x4040>;
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