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drm/i915/dg2: add DG2 UHBR source rates

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DG2 supports DP 2.0 UHBR and 128b/132b channel encoding.

Bspec: 53657, 54034
Acked-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/8f82b7eb76f20f1c4ddd2cc7d1bb31e2173c55a6.1629735412.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2021-08-23 19:18:11 +03:00
parent 1db18260f1
commit e752d1f9c1
1 changed files with 9 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
drivers/gpu/drm/i915/display/intel_dp.c
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@ -242,6 +242,11 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
encoder->port != PORT_A);
}
static int dg2_max_source_rate(struct intel_dp *intel_dp)
{
return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
}
static int icl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@ -268,7 +273,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
/* The values must be in increasing order */
static const int icl_rates[] = {
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
1000000, 1350000,
};
static const int bxt_rates[] = {
162000, 216000, 243000, 270000, 324000, 432000, 540000
@ -295,6 +301,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 11) {
source_rates = icl_rates;
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
max_rate = dg2_max_source_rate(intel_dp);
if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
else