drm/i915/dg2: add DG2 UHBR source rates
DG2 supports DP 2.0 UHBR and 128b/132b channel encoding. Bspec: 53657, 54034 Acked-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8f82b7eb76f20f1c4ddd2cc7d1bb31e2173c55a6.1629735412.git.jani.nikula@intel.com
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1 changed files with 9 additions and 1 deletions
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@ -242,6 +242,11 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
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encoder->port != PORT_A);
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encoder->port != PORT_A);
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}
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}
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static int dg2_max_source_rate(struct intel_dp *intel_dp)
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{
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return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
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}
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static int icl_max_source_rate(struct intel_dp *intel_dp)
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static int icl_max_source_rate(struct intel_dp *intel_dp)
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{
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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@ -268,7 +273,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
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{
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{
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/* The values must be in increasing order */
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/* The values must be in increasing order */
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static const int icl_rates[] = {
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static const int icl_rates[] = {
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162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
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162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
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1000000, 1350000,
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};
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};
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static const int bxt_rates[] = {
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static const int bxt_rates[] = {
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162000, 216000, 243000, 270000, 324000, 432000, 540000
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162000, 216000, 243000, 270000, 324000, 432000, 540000
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@ -295,6 +301,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
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if (DISPLAY_VER(dev_priv) >= 11) {
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if (DISPLAY_VER(dev_priv) >= 11) {
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source_rates = icl_rates;
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source_rates = icl_rates;
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size = ARRAY_SIZE(icl_rates);
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size = ARRAY_SIZE(icl_rates);
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if (IS_DG2(dev_priv))
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max_rate = dg2_max_source_rate(intel_dp);
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if (IS_JSL_EHL(dev_priv))
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if (IS_JSL_EHL(dev_priv))
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max_rate = ehl_max_source_rate(intel_dp);
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max_rate = ehl_max_source_rate(intel_dp);
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else
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else
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