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drm/amdgpu: detect current GPU memory partition mode

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- Add helpers to detect the current GPU memory partition.
 - Add current memory partition mode sysfs node.

Tested-by: Ori Messinger <Ori.Messinger@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rajneesh Bhardwaj 2022-04-05 13:00:13 -04:00 • committed by Alex Deucher
parent 6b7ec18b04
commit ea2d2f8ece
5 changed files with 60 additions and 0 deletions
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25
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
View file

@ -1200,6 +1200,24 @@ static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
return sysfs_emit(buf, "%s\n", partition_mode);
}
static ssize_t amdgpu_gfx_get_current_memory_partition(struct device *dev,
struct device_attribute *addr,
char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
enum amdgpu_memory_partition mode;
static const char *partition_modes[] = {
"UNKNOWN", "NPS1", "NPS2", "NPS4", "NPS8"
};
BUILD_BUG_ON(ARRAY_SIZE(partition_modes) <= AMDGPU_NPS8_PARTITION_MODE);
mode = min((int)adev->gfx.funcs->query_mem_partition_mode(adev),
AMDGPU_NPS8_PARTITION_MODE);
return sysfs_emit(buf, "%s\n", partition_modes[mode]);
}
static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
struct device_attribute *addr,
const char *buf, size_t count)
@ -1307,6 +1325,9 @@ static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
static DEVICE_ATTR(available_compute_partition, S_IRUGO,
amdgpu_gfx_get_available_compute_partition, NULL);
static DEVICE_ATTR(current_memory_partition, S_IRUGO,
amdgpu_gfx_get_current_memory_partition, NULL);
int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
{
int r;
@ -1319,5 +1340,9 @@ int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
if (r)
return r;
r = device_create_file(adev->dev, &dev_attr_current_memory_partition);
if (r)
return r;
return 0;
}

11
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
View file

@ -71,6 +71,14 @@ enum amdgpu_pkg_type {
AMDGPU_PKG_TYPE_UNKNOWN,
};
enum amdgpu_memory_partition {
UNKNOWN_MEMORY_PARTITION_MODE = 0,
AMDGPU_NPS1_PARTITION_MODE = 1,
AMDGPU_NPS2_PARTITION_MODE = 2,
AMDGPU_NPS4_PARTITION_MODE = 3,
AMDGPU_NPS8_PARTITION_MODE = 4,
};
struct amdgpu_mec {
struct amdgpu_bo *hpd_eop_obj;
u64 hpd_eop_gpu_addr;
@ -268,6 +276,8 @@ struct amdgpu_gfx_funcs {
struct amdgpu_gfx_shadow_info *shadow_info);
enum amdgpu_gfx_partition
(*query_partition_mode)(struct amdgpu_device *adev);
enum amdgpu_memory_partition
(*query_mem_partition_mode)(struct amdgpu_device *adev);
int (*switch_partition_mode)(struct amdgpu_device *adev,
enum amdgpu_gfx_partition mode);
};
@ -404,6 +414,7 @@ struct amdgpu_gfx {
enum amdgpu_gfx_partition partition_mode;
uint16_t xcc_mask;
enum amdgpu_memory_partition mem_partition_mode;
uint32_t num_xcc_per_xcp;
struct mutex partition_mutex;
};

1
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
View file

@ -97,6 +97,7 @@ struct amdgpu_nbio_funcs {
void (*clear_doorbell_interrupt)(struct amdgpu_device *adev);
u32 (*get_rom_offset)(struct amdgpu_device *adev);
u32 (*get_compute_partition_mode)(struct amdgpu_device *adev);
u32 (*get_memory_partition_mode)(struct amdgpu_device *adev);
void (*set_compute_partition_mode)(struct amdgpu_device *adev,
enum amdgpu_gfx_partition mode);
};

11
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
View file

@ -606,6 +606,16 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
{
soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
}
static enum amdgpu_memory_partition
gfx_v9_4_3_query_memory_partition(struct amdgpu_device *adev)
{
enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
if (adev->nbio.funcs->get_memory_partition_mode)
mode = adev->nbio.funcs->get_memory_partition_mode(adev);
return mode;
}
static enum amdgpu_gfx_partition
gfx_v9_4_3_query_compute_partition(struct amdgpu_device *adev)
@ -675,6 +685,7 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
.select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
.query_partition_mode = &gfx_v9_4_3_query_compute_partition,
.switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
.query_mem_partition_mode = &gfx_v9_4_3_query_memory_partition,
};
static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)

12
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
View file

@ -30,6 +30,8 @@
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
#include <uapi/linux/kfd_ioctl.h>
#define NPS_MODE_MASK 0x000000FFL
static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@ -406,6 +408,15 @@ static void nbio_v7_9_set_compute_partition_mode(struct amdgpu_device *adev,
WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS, tmp);
}
static enum amdgpu_memory_partition nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev)
{
u32 tmp;
tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
return ffs(tmp);
}
const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
.get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
@ -428,4 +439,5 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
.set_compute_partition_mode = nbio_v7_9_set_compute_partition_mode,
.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
};