arm64: tegra: Add memory controller on Tegra234
This adds the memory controller and the embedded external memory controller found on the Tegra234 SoC. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -3,6 +3,7 @@
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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/ {
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@ -84,6 +85,54 @@
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gpio-controller;
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};
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mc: memory-controller@2c00000 {
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compatible = "nvidia,tegra234-mc";
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reg = <0x02c00000 0x100000>,
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<0x02b80000 0x040000>,
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<0x01700000 0x100000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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#interconnect-cells = <1>;
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status = "okay";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
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<0x02b80000 0x0 0x02b80000 0x0 0x040000>,
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<0x02c00000 0x0 0x02c00000 0x0 0x100000>;
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/*
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* Bit 39 of addresses passing through the memory
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* controller selects the XBAR format used when memory
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* is accessed. This is used to transparently access
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* memory in the XBAR format used by the discrete GPU
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* (bit 39 set) or Tegra (bit 39 clear).
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*
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* As a consequence, the operating system must ensure
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* that bit 39 is never used implicitly, for example
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* via an I/O virtual address mapping of an IOMMU. If
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* devices require access to the XBAR switch, their
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* drivers must set this bit explicitly.
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*
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* Limit the DMA range for memory clients to [38:0].
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*/
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dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
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emc: external-memory-controller@2c60000 {
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compatible = "nvidia,tegra234-emc";
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reg = <0x0 0x02c60000 0x0 0x90000>,
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<0x0 0x01780000 0x0 0x80000>;
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interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA234_CLK_EMC>;
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clock-names = "emc";
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status = "okay";
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#interconnect-cells = <0>;
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nvidia,bpmp = <&bpmp>;
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};
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
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reg = <0x03100000 0x10000>;
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