Fix miscellaneous irqchip bugs.
Signed-off-by: Ingo Molnar <mingo@kernel.org> -----BEGIN PGP SIGNATURE----- iQJFBAABCgAvFiEEBpT5eoXrXCwVQwEKEnMQ0APhK1gFAme51TARHG1pbmdvQGtl cm5lbC5vcmcACgkQEnMQ0APhK1i9gg/+O/yXZ8k/2hl4Kc7NvlhszHDNRLht6Sd9 ZdRtn6N6yY5JkQhGEzXv/gFVRJWtxHwOF7cHJysgqRzsv4YFufqSMZN3CaMnbKOd ZgK3Kmt0YunamEvdKDrJJ6oPN0Ul7f4ipcD9qfuh2TM2YrLzBwTKuMR5ZEASEmgn yF3FqDHTyqdhUi/ti5HKRcF4ElWh0ATALeHtjDmVWQq4pv7bsOOu5F438ZIomVPF r+2R9M1nPghozZ00wHcsn86TyEWcF63TVKLoDrTG+mC3xyFOwoP+E/P20Kad6V3f 14IhQyVteClUy7BwD5mSPZ86s52t1RQngaQF8ofDiEipUFP5/AsLsTAtzy/rOaPg PheHVdYNNuxxRW63pJHpAGr+sWYGT4eYAWBodF6VxWmDNtLeKDf2MQyNW6Ip3QqF l9FADyyCl4ItyU65py1W0oAbdhSzN7qIco30flWlIv6t6QLPTORmob6ogY5r2Npj fn0/lHBkR2/cDlK0EV3JoFgy6AI58t+ThvvEXBfj7a7pxDve7Li5X2U6Hw7lSbn5 3r6URYXn4jUERV9+vMPGBvrXpeE+itDzT3NDl1Qm7uHq22k9o8TaLEgUD7tq/K0V a2HKxsDaqi0esdVM2bndVKBRsjgSOkt+jhmppmQd4PJ4GfjZxT9egdgn6GVs6WtI VOPejBKFBpM= =Kfhc -----END PGP SIGNATURE----- Merge tag 'irq-urgent-2025-02-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Ingo Molnar: "Fix miscellaneous irqchip bugs" * tag 'irq-urgent-2025-02-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/qcom-pdc: Workaround hardware register bug on X1E80100 irqchip/jcore-aic, clocksource/drivers/jcore: Fix jcore-pit interrupt request irqchip/gic-v3: Fix rk3399 workaround when secure interrupts are enabled
This commit is contained in:
Linus Torvalds
commit
f112eea3cc
4 changed files with 117 additions and 16 deletions
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@ -114,6 +114,18 @@ static int jcore_pit_local_init(unsigned cpu)
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pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);
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clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);
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enable_percpu_irq(pit->ced.irq, IRQ_TYPE_NONE);
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return 0;
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}
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static int jcore_pit_local_teardown(unsigned cpu)
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{
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struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
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pr_info("Local J-Core PIT teardown on cpu %u\n", cpu);
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disable_percpu_irq(pit->ced.irq);
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return 0;
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}
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@ -168,6 +180,7 @@ static int __init jcore_pit_init(struct device_node *node)
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return -ENOMEM;
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}
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irq_set_percpu_devid(pit_irq);
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err = request_percpu_irq(pit_irq, jcore_timer_interrupt,
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"jcore_pit", jcore_pit_percpu);
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if (err) {
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@ -237,7 +250,7 @@ static int __init jcore_pit_init(struct device_node *node)
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cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,
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"clockevents/jcore:starting",
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jcore_pit_local_init, NULL);
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jcore_pit_local_init, jcore_pit_local_teardown);
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return 0;
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}
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@ -44,6 +44,7 @@ static u8 dist_prio_nmi __ro_after_init = GICV3_PRIO_NMI;
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#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
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#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
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#define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2)
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#define FLAGS_WORKAROUND_INSECURE (1ULL << 3)
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#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
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@ -83,6 +84,8 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
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#define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
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#define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
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static bool nmi_support_forbidden;
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/*
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* There are 16 SGIs, though we only actually use 8 in Linux. The other 8 SGIs
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* are potentially stolen by the secure side. Some code, especially code dealing
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@ -163,21 +166,27 @@ static void __init gic_prio_init(void)
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{
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bool ds;
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cpus_have_group0 = gic_has_group0();
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ds = gic_dist_security_disabled();
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if (!ds) {
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u32 val;
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if ((gic_data.flags & FLAGS_WORKAROUND_INSECURE) && !ds) {
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if (cpus_have_group0) {
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u32 val;
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val = readl_relaxed(gic_data.dist_base + GICD_CTLR);
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val |= GICD_CTLR_DS;
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writel_relaxed(val, gic_data.dist_base + GICD_CTLR);
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val = readl_relaxed(gic_data.dist_base + GICD_CTLR);
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val |= GICD_CTLR_DS;
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writel_relaxed(val, gic_data.dist_base + GICD_CTLR);
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ds = gic_dist_security_disabled();
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if (ds)
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pr_warn("Broken GIC integration, security disabled");
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ds = gic_dist_security_disabled();
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if (ds)
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pr_warn("Broken GIC integration, security disabled\n");
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} else {
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pr_warn("Broken GIC integration, pNMI forbidden\n");
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nmi_support_forbidden = true;
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}
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}
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cpus_have_security_disabled = ds;
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cpus_have_group0 = gic_has_group0();
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/*
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* How priority values are used by the GIC depends on two things:
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@ -209,7 +218,7 @@ static void __init gic_prio_init(void)
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* be in the non-secure range, we program the non-secure values into
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* the distributor to match the PMR values we want.
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*/
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if (cpus_have_group0 & !cpus_have_security_disabled) {
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if (cpus_have_group0 && !cpus_have_security_disabled) {
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dist_prio_irq = __gicv3_prio_to_ns(dist_prio_irq);
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dist_prio_nmi = __gicv3_prio_to_ns(dist_prio_nmi);
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}
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@ -1922,6 +1931,18 @@ static bool gic_enable_quirk_arm64_2941627(void *data)
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return true;
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}
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static bool gic_enable_quirk_rk3399(void *data)
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{
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struct gic_chip_data *d = data;
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if (of_machine_is_compatible("rockchip,rk3399")) {
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d->flags |= FLAGS_WORKAROUND_INSECURE;
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return true;
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}
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return false;
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}
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static bool rd_set_non_coherent(void *data)
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{
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struct gic_chip_data *d = data;
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@ -1996,6 +2017,12 @@ static const struct gic_quirk gic_quirks[] = {
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.property = "dma-noncoherent",
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.init = rd_set_non_coherent,
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},
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{
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.desc = "GICv3: Insecure RK3399 integration",
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.iidr = 0x0000043b,
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.mask = 0xff000fff,
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.init = gic_enable_quirk_rk3399,
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},
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{
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}
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};
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@ -2004,7 +2031,7 @@ static void gic_enable_nmi_support(void)
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{
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int i;
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if (!gic_prio_masking_enabled())
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if (!gic_prio_masking_enabled() || nmi_support_forbidden)
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return;
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rdist_nmi_refs = kcalloc(gic_data.ppi_nr + SGI_NR,
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@ -38,7 +38,7 @@ static struct irq_chip jcore_aic;
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static void handle_jcore_irq(struct irq_desc *desc)
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{
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if (irqd_is_per_cpu(irq_desc_get_irq_data(desc)))
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handle_percpu_irq(desc);
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handle_percpu_devid_irq(desc);
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else
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handle_simple_irq(desc);
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}
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@ -21,9 +21,11 @@
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#include <linux/types.h>
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#define PDC_MAX_GPIO_IRQS 256
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#define PDC_DRV_OFFSET 0x10000
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/* Valid only on HW version < 3.2 */
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#define IRQ_ENABLE_BANK 0x10
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#define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_IRQS))
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#define IRQ_i_CFG 0x110
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/* Valid only on HW version >= 3.2 */
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@ -46,13 +48,20 @@ struct pdc_pin_region {
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static DEFINE_RAW_SPINLOCK(pdc_lock);
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static void __iomem *pdc_base;
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static void __iomem *pdc_prev_base;
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static struct pdc_pin_region *pdc_region;
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static int pdc_region_cnt;
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static unsigned int pdc_version;
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static bool pdc_x1e_quirk;
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static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val)
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{
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writel_relaxed(val, base + reg + i * sizeof(u32));
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}
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static void pdc_reg_write(int reg, u32 i, u32 val)
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{
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writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
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pdc_base_reg_write(pdc_base, reg, i, val);
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}
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static u32 pdc_reg_read(int reg, u32 i)
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@ -60,6 +69,34 @@ static u32 pdc_reg_read(int reg, u32 i)
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return readl_relaxed(pdc_base + reg + i * sizeof(u32));
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}
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static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)
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{
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void __iomem *base;
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/* Remap the write access to work around a hardware bug on X1E */
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switch (bank) {
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case 0 ... 1:
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/* Use previous DRV (client) region and shift to bank 3-4 */
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base = pdc_prev_base;
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bank += 3;
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break;
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case 2 ... 4:
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/* Use our own region and shift to bank 0-2 */
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base = pdc_base;
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bank -= 2;
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break;
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case 5:
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/* No fixup required for bank 5 */
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base = pdc_base;
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break;
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default:
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WARN_ON(1);
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return;
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}
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pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable);
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}
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static void __pdc_enable_intr(int pin_out, bool on)
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{
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unsigned long enable;
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@ -72,7 +109,11 @@ static void __pdc_enable_intr(int pin_out, bool on)
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enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
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__assign_bit(mask, &enable, on);
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pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
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if (pdc_x1e_quirk)
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pdc_x1e_irq_enable_write(index, enable);
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else
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pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
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} else {
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enable = pdc_reg_read(IRQ_i_CFG, pin_out);
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__assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);
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@ -324,10 +365,29 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
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if (res_size > resource_size(&res))
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pr_warn("%pOF: invalid reg size, please fix DT\n", node);
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/*
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* PDC has multiple DRV regions, each one provides the same set of
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* registers for a particular client in the system. Due to a hardware
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* bug on X1E, some writes to the IRQ_ENABLE_BANK register must be
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* issued inside the previous region. This region belongs to
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* a different client and is not described in the device tree. Map the
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* region with the expected offset to preserve support for old DTs.
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*/
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if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) {
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pdc_prev_base = ioremap(res.start - PDC_DRV_OFFSET, IRQ_ENABLE_BANK_MAX);
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if (!pdc_prev_base) {
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pr_err("%pOF: unable to map previous PDC DRV region\n", node);
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return -ENXIO;
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}
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pdc_x1e_quirk = true;
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}
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pdc_base = ioremap(res.start, res_size);
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if (!pdc_base) {
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pr_err("%pOF: unable to map PDC registers\n", node);
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return -ENXIO;
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ret = -ENXIO;
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goto fail;
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}
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pdc_version = pdc_reg_read(PDC_VERSION_REG, 0);
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@ -363,6 +423,7 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
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fail:
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kfree(pdc_region);
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iounmap(pdc_base);
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iounmap(pdc_prev_base);
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return ret;
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}
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