ASoC: codecs: lpass-rx-macro: add iir widgets
This patch adds iir widgets and mixers on this codec Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210211122735.5691-5-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivas Kandagatla
Mark Brown
parent
4f692926f5
commit
f3ce6f3c9a
1 changed files with 264 additions and 0 deletions
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@ -525,6 +525,38 @@ enum {
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INTERP_MIX_PATH,
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INTERP_MIX_PATH,
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};
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};
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/* Codec supports 2 IIR filters */
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enum {
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IIR0 = 0,
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IIR1,
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IIR_MAX,
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};
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/* Each IIR has 5 Filter Stages */
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enum {
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BAND1 = 0,
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BAND2,
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BAND3,
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BAND4,
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BAND5,
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BAND_MAX,
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};
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#define RX_MACRO_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
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#define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = rx_macro_iir_filter_info, \
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.get = rx_macro_get_iir_band_audio_mixer, \
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.put = rx_macro_put_iir_band_audio_mixer, \
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.private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
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.iir_idx = iidx, \
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.band_idx = bidx, \
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.bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \
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} \
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}
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struct interp_sample_rate {
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struct interp_sample_rate {
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int sample_rate;
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int sample_rate;
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int rate_val;
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int rate_val;
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@ -581,6 +613,12 @@ struct rx_macro {
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};
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};
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#define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
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#define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
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struct wcd_iir_filter_ctl {
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unsigned int iir_idx;
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unsigned int band_idx;
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struct soc_bytes_ext bytes_ext;
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};
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static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
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static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
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static const char * const rx_int_mix_mux_text[] = {
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static const char * const rx_int_mix_mux_text[] = {
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@ -2596,6 +2634,166 @@ static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
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return 0;
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return 0;
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}
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}
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static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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switch (event) {
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case SND_SOC_DAPM_POST_PMU: /* fall through */
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case SND_SOC_DAPM_PRE_PMD:
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if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
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} else {
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
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snd_soc_component_write(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
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snd_soc_component_read(component,
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
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}
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break;
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}
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return 0;
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}
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static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
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int iir_idx, int band_idx, int coeff_idx)
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{
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u32 value;
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int reg, b2_reg;
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/* Address does not automatically update if reading */
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reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
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b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
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snd_soc_component_write(component, reg,
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((band_idx * BAND_MAX + coeff_idx) *
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sizeof(uint32_t)) & 0x7F);
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value = snd_soc_component_read(component, b2_reg);
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snd_soc_component_write(component, reg,
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((band_idx * BAND_MAX + coeff_idx)
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* sizeof(uint32_t) + 1) & 0x7F);
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value |= (snd_soc_component_read(component, b2_reg) << 8);
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snd_soc_component_write(component, reg,
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((band_idx * BAND_MAX + coeff_idx)
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* sizeof(uint32_t) + 2) & 0x7F);
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value |= (snd_soc_component_read(component, b2_reg) << 16);
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snd_soc_component_write(component, reg,
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((band_idx * BAND_MAX + coeff_idx)
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* sizeof(uint32_t) + 3) & 0x7F);
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/* Mask bits top 2 bits since they are reserved */
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value |= (snd_soc_component_read(component, b2_reg) << 24);
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return value;
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}
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static void set_iir_band_coeff(struct snd_soc_component *component,
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int iir_idx, int band_idx, uint32_t value)
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{
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int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
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snd_soc_component_write(component, reg, (value & 0xFF));
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snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
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snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
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/* Mask top 2 bits, 7-8 are reserved */
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snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
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}
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static int rx_macro_put_iir_band_audio_mixer(
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struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct wcd_iir_filter_ctl *ctl =
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(struct wcd_iir_filter_ctl *)kcontrol->private_value;
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struct soc_bytes_ext *params = &ctl->bytes_ext;
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int iir_idx = ctl->iir_idx;
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int band_idx = ctl->band_idx;
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u32 coeff[BAND_MAX];
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int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
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memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
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/* Mask top bit it is reserved */
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/* Updates addr automatically for each B2 write */
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snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
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sizeof(uint32_t)) & 0x7F);
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set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
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set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
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set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
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set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
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set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
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return 0;
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}
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static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct wcd_iir_filter_ctl *ctl =
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(struct wcd_iir_filter_ctl *)kcontrol->private_value;
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struct soc_bytes_ext *params = &ctl->bytes_ext;
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int iir_idx = ctl->iir_idx;
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int band_idx = ctl->band_idx;
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u32 coeff[BAND_MAX];
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coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
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coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
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coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
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coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
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coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
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memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
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return 0;
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}
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static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *ucontrol)
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{
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struct wcd_iir_filter_ctl *ctl =
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(struct wcd_iir_filter_ctl *)kcontrol->private_value;
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struct soc_bytes_ext *params = &ctl->bytes_ext;
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ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
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ucontrol->count = params->max;
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return 0;
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}
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static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
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static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
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SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
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SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
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-84, 40, digital_gain),
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-84, 40, digital_gain),
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@ -2630,6 +2828,65 @@ static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
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SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
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SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
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rx_macro_aux_hpf_mode_get,
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rx_macro_aux_hpf_mode_get,
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rx_macro_aux_hpf_mode_put),
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rx_macro_aux_hpf_mode_put),
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SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
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CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
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CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
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digital_gain),
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SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
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0, 1, 0),
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SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
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1, 1, 0),
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SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
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2, 1, 0),
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SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
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3, 1, 0),
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SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
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4, 1, 0),
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SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
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0, 1, 0),
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SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
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1, 1, 0),
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SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
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2, 1, 0),
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SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
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3, 1, 0),
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SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
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4, 1, 0),
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RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
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RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
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RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
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RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
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RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
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RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
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RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
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RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
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RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
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RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
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};
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};
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static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
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static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
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@ -2725,6 +2982,13 @@ static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
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RX_MACRO_EC2_MUX, 0,
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RX_MACRO_EC2_MUX, 0,
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&rx_mix_tx2_mux, rx_macro_enable_echo,
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&rx_mix_tx2_mux, rx_macro_enable_echo,
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SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
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SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
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SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
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4, 0, NULL, 0, rx_macro_set_iir_gain,
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SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
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SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL,
|
||||||
|
4, 0, NULL, 0, rx_macro_set_iir_gain,
|
||||||
|
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
|
||||||
SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
|
SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
|
||||||
4, 0, NULL, 0),
|
4, 0, NULL, 0),
|
||||||
SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
|
SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue