nfp: bpf: support arithmetic right shift by constant (BPF_ARSH | BPF_K)
Code logic is similar with logic right shift except we also need to set PREV_ALU result properly, the MSB of which is the bit that will be replicated to fill in all the vacant positions. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
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2 changed files with 35 additions and 0 deletions
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@ -1916,6 +1916,39 @@ static int shr_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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return 0;
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return 0;
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}
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}
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/* Code logic is the same as __shr_imm64 except ashr requires signedness bit
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* told through PREV_ALU result.
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*/
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static int ashr_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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const struct bpf_insn *insn = &meta->insn;
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u8 dst = insn->dst_reg * 2;
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if (insn->imm < 32) {
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emit_shf(nfp_prog, reg_both(dst), reg_a(dst + 1), SHF_OP_NONE,
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reg_b(dst), SHF_SC_R_DSHF, insn->imm);
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/* Set signedness bit. */
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emit_alu(nfp_prog, reg_none(), reg_a(dst + 1), ALU_OP_OR,
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reg_imm(0));
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emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR,
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reg_b(dst + 1), SHF_SC_R_SHF, insn->imm);
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} else if (insn->imm == 32) {
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/* NOTE: this also helps setting signedness bit. */
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wrp_reg_mov(nfp_prog, dst, dst + 1);
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emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR,
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reg_b(dst + 1), SHF_SC_R_SHF, 31);
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} else if (insn->imm > 32) {
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emit_alu(nfp_prog, reg_none(), reg_a(dst + 1), ALU_OP_OR,
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reg_imm(0));
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emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR,
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reg_b(dst + 1), SHF_SC_R_SHF, insn->imm - 32);
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emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR,
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reg_b(dst + 1), SHF_SC_R_SHF, 31);
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}
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return 0;
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}
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static int mov_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int mov_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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{
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const struct bpf_insn *insn = &meta->insn;
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const struct bpf_insn *insn = &meta->insn;
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@ -2742,6 +2775,7 @@ static const instr_cb_t instr_cb[256] = {
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[BPF_ALU64 | BPF_LSH | BPF_K] = shl_imm64,
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[BPF_ALU64 | BPF_LSH | BPF_K] = shl_imm64,
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[BPF_ALU64 | BPF_RSH | BPF_X] = shr_reg64,
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[BPF_ALU64 | BPF_RSH | BPF_X] = shr_reg64,
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[BPF_ALU64 | BPF_RSH | BPF_K] = shr_imm64,
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[BPF_ALU64 | BPF_RSH | BPF_K] = shr_imm64,
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[BPF_ALU64 | BPF_ARSH | BPF_K] = ashr_imm64,
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[BPF_ALU | BPF_MOV | BPF_X] = mov_reg,
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[BPF_ALU | BPF_MOV | BPF_X] = mov_reg,
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[BPF_ALU | BPF_MOV | BPF_K] = mov_imm,
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[BPF_ALU | BPF_MOV | BPF_K] = mov_imm,
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[BPF_ALU | BPF_XOR | BPF_X] = xor_reg,
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[BPF_ALU | BPF_XOR | BPF_X] = xor_reg,
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@ -174,6 +174,7 @@ enum shf_op {
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SHF_OP_NONE = 0,
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SHF_OP_NONE = 0,
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SHF_OP_AND = 2,
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SHF_OP_AND = 2,
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SHF_OP_OR = 5,
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SHF_OP_OR = 5,
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SHF_OP_ASHR = 6,
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};
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};
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enum shf_sc {
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enum shf_sc {
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