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drm/amd/display: Add NULL test for 'timing generator' in 'dcn21_set_pipe()'

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In "u32 otg_inst = pipe_ctx->stream_res.tg->inst;"
pipe_ctx->stream_res.tg could be NULL, it is relying on the caller to
ensure the tg is not NULL.

Fixes: 474ac4a875 ("drm/amd/display: Implement some asic specific abm call backs.")
Cc: Yongqiang Sun <yongqiang.sun@amd.com>
Cc: Anthony Koo <Anthony.Koo@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Srinivasan Shanmugam 2024-01-31 08:49:41 +05:30 • committed by Alex Deucher
parent 886571d217
commit fb5a3d0370
1 changed files with 14 additions and 10 deletions
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24
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
View file

@ -206,28 +206,32 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
void dcn21_set_pipe(struct pipe_ctx *pipe_ctx) void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)
{ {
struct abm *abm = pipe_ctx->stream_res.abm; struct abm *abm = pipe_ctx->stream_res.abm;
uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; struct timing_generator *tg = pipe_ctx->stream_res.tg;
struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;
uint32_t otg_inst;
if (!abm && !tg && !panel_cntl)
return;
otg_inst = tg->inst;
if (dmcu) { if (dmcu) {
dce110_set_pipe(pipe_ctx); dce110_set_pipe(pipe_ctx);
return; return;
} }
if (abm && panel_cntl) { if (abm->funcs && abm->funcs->set_pipe_ex) {
if (abm->funcs && abm->funcs->set_pipe_ex) { abm->funcs->set_pipe_ex(abm,
abm->funcs->set_pipe_ex(abm,
otg_inst, otg_inst,
SET_ABM_PIPE_NORMAL, SET_ABM_PIPE_NORMAL,
panel_cntl->inst, panel_cntl->inst,
panel_cntl->pwrseq_inst); panel_cntl->pwrseq_inst);
} else { } else {
dmub_abm_set_pipe(abm, otg_inst, dmub_abm_set_pipe(abm, otg_inst,
SET_ABM_PIPE_NORMAL, SET_ABM_PIPE_NORMAL,
panel_cntl->inst, panel_cntl->inst,
panel_cntl->pwrseq_inst); panel_cntl->pwrseq_inst);
}
} }
} }