clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}()
All clocks in this driver are supported by the common simple probe mechanism and it's now possible to migrate to it. While at it, also switch to using the module_platform_driver() macro. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-15-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
Stephen Boyd
parent
ff96210073
commit
ffe91cb28f
1 changed files with 37 additions and 204 deletions
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@ -752,220 +752,53 @@ static const struct mtk_gate peri_clks[] = {
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&mtk_clk_gate_ops_no_setclr),
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&mtk_clk_gate_ops_no_setclr),
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};
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};
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static int clk_mt8365_top_probe(struct platform_device *pdev)
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static const struct mtk_clk_desc topck_desc = {
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{
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.clks = top_clk_gates,
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void __iomem *base;
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.num_clks = ARRAY_SIZE(top_clk_gates),
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struct clk_hw_onecell_data *clk_data;
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.fixed_clks = top_fixed_clks,
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struct device_node *node = pdev->dev.of_node;
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.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
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struct device *dev = &pdev->dev;
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.factor_clks = top_divs,
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int ret;
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.num_factor_clks = ARRAY_SIZE(top_divs),
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int i;
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.mux_clks = top_muxes,
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.num_mux_clks = ARRAY_SIZE(top_muxes),
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base = devm_platform_ioremap_resource(pdev, 0);
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.composite_clks = top_misc_muxes,
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if (IS_ERR(base))
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.num_composite_clks = ARRAY_SIZE(top_misc_muxes),
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return PTR_ERR(base);
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.divider_clks = top_adj_divs,
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.num_divider_clks = ARRAY_SIZE(top_adj_divs),
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clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
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.clk_lock = &mt8365_clk_lock,
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_clk_register_fixed_clks(top_fixed_clks,
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ARRAY_SIZE(top_fixed_clks), clk_data);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
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clk_data);
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if (ret)
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goto unregister_fixed_clks;
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ret = mtk_clk_register_muxes(&pdev->dev, top_muxes,
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ARRAY_SIZE(top_muxes), node,
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&mt8365_clk_lock, clk_data);
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if (ret)
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goto unregister_factors;
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ret = mtk_clk_register_composites(&pdev->dev, top_misc_muxes,
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ARRAY_SIZE(top_misc_muxes), base,
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&mt8365_clk_lock, clk_data);
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if (ret)
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goto unregister_muxes;
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ret = mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
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base, &mt8365_clk_lock, clk_data);
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if (ret)
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goto unregister_composites;
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ret = mtk_clk_register_gates(&pdev->dev, node, top_clk_gates,
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ARRAY_SIZE(top_clk_gates), clk_data);
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if (ret)
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goto unregister_dividers;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_gates;
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return 0;
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unregister_gates:
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mtk_clk_unregister_gates(top_clk_gates, ARRAY_SIZE(top_clk_gates), clk_data);
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unregister_dividers:
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mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
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clk_data);
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unregister_composites:
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mtk_clk_unregister_composites(top_misc_muxes,
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ARRAY_SIZE(top_misc_muxes), clk_data);
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unregister_muxes:
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mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data);
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unregister_factors:
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mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
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unregister_fixed_clks:
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mtk_clk_unregister_fixed_clks(top_fixed_clks,
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ARRAY_SIZE(top_fixed_clks), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static int clk_mt8365_infra_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int ret;
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clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_clk_register_gates(&pdev->dev, node, ifr_clks,
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ARRAY_SIZE(ifr_clks), clk_data);
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if (ret)
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goto free_clk_data;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_gates;
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return 0;
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unregister_gates:
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mtk_clk_unregister_gates(ifr_clks, ARRAY_SIZE(ifr_clks), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static int clk_mt8365_peri_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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struct clk_hw_onecell_data *clk_data;
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_devm_alloc_clk_data(dev, CLK_PERI_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_clk_register_gates(&pdev->dev, node, peri_clks,
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ARRAY_SIZE(peri_clks), clk_data);
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if (ret)
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return ret;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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return ret;
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}
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static int clk_mt8365_mcu_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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void __iomem *base;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
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ARRAY_SIZE(mcu_muxes), base,
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&mt8365_clk_lock, clk_data);
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if (ret)
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goto free_clk_data;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_composites;
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return 0;
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unregister_composites:
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mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes),
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clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static const struct of_device_id of_match_clk_mt8365[] = {
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{
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.compatible = "mediatek,mt8365-topckgen",
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.data = clk_mt8365_top_probe,
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}, {
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.compatible = "mediatek,mt8365-infracfg",
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.data = clk_mt8365_infra_probe,
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}, {
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.compatible = "mediatek,mt8365-pericfg",
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.data = clk_mt8365_peri_probe,
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}, {
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.compatible = "mediatek,mt8365-mcucfg",
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.data = clk_mt8365_mcu_probe,
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}, {
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/* sentinel */
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}
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};
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};
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static int clk_mt8365_probe(struct platform_device *pdev)
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static const struct mtk_clk_desc infra_desc = {
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{
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.clks = ifr_clks,
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int (*clk_probe)(struct platform_device *pdev);
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.num_clks = ARRAY_SIZE(ifr_clks),
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int ret;
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};
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clk_probe = of_device_get_match_data(&pdev->dev);
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static const struct mtk_clk_desc peri_desc = {
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if (!clk_probe)
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.clks = peri_clks,
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return -EINVAL;
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.num_clks = ARRAY_SIZE(peri_clks),
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};
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ret = clk_probe(pdev);
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static const struct mtk_clk_desc mcu_desc = {
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if (ret)
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.composite_clks = mcu_muxes,
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dev_err(&pdev->dev,
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.num_composite_clks = ARRAY_SIZE(mcu_muxes),
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"%s: could not register clock provider: %d\n",
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.clk_lock = &mt8365_clk_lock,
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pdev->name, ret);
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};
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return ret;
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static const struct of_device_id of_match_clk_mt8365[] = {
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}
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{ .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc },
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{ .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc },
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{ .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc },
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{ .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt8365_drv = {
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static struct platform_driver clk_mt8365_drv = {
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.probe = clk_mt8365_probe,
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.driver = {
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.driver = {
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.name = "clk-mt8365",
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.name = "clk-mt8365",
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.of_match_table = of_match_clk_mt8365,
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.of_match_table = of_match_clk_mt8365,
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},
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},
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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};
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};
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module_platform_driver(clk_mt8365_drv);
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static int __init clk_mt8365_init(void)
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{
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return platform_driver_register(&clk_mt8365_drv);
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}
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arch_initcall(clk_mt8365_init);
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MODULE_LICENSE("GPL");
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MODULE_LICENSE("GPL");
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