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13 commits

Author SHA1 Message Date
Ben Skeggs
7a4dde711b drm/nouveau/secboot: move code to boot LS falcons to subdevs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:29 +10:00
Ben Skeggs
e1cc579898 drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:29 +10:00
Ben Skeggs
d114a1393f drm/nouveau/flcn/msgq: move handling of init message to subdevs
When the PMU/SEC2 LS FWs have booted, they'll send a message to the host
with various information, including the configuration of message/command
queues that are available.

Move the handling for this to the relevant subdevs.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:29 +10:00
Ben Skeggs
22431189d6 drm/nouveau/flcn/msgq: explicitly create message queue from subdevs
Code to interface with LS firmwares is being moved to the subdevs where it
belongs, rather than living in the common falcon code.

This is an incremental step towards that goal.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:28 +10:00
Ben Skeggs
acc466ab46 drm/nouveau/flcn/cmdq: explicitly create command queue(s) from subdevs
Code to interface with LS firmwares is being moved to the subdevs where it
belongs, rather than living in the common falcon code.

This is an incremental step towards that goal.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:28 +10:00
Ben Skeggs
8763955ba7 drm/nouveau/flcn/qmgr: explicitly create queue manager from subdevs
Code to interface with LS firmwares is being moved to the subdevs where it
belongs, rather than living in the common falcon code.

This is an incremental step towards that goal.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:28 +10:00
Ben Skeggs
c9af47bcbd drm/nouveau/sec2: move interrupt handler to hw-specific module
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:27 +10:00
Ben Skeggs
555a0002d3 drm/nouveau/sec2: use falcon funcs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:27 +10:00
Ben Skeggs
edd757d178 drm/nouveau/sec2: initialise SW state for falcon from constructor
This will allow us to register the falcon with ACR, and further customise
its behaviour by providing the nvkm_falcon_func structure directly.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:27 +10:00
Ben Skeggs
7adc40c593 drm/nouveau/sec2: select implementation based on available firmware
This will allow for further customisation of the subdev depending on what
firmware is available.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:27 +10:00
Ben Skeggs
fdad518362 drm/nouveau/sec2: utilise engine PRI address from TOP
Turing has its SEC2 instance in an alternate location, and this avoids
needing to duplicate the code here for it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:59 +10:00
Alexandre Courbot
b7d6c8db49 drm/nouveau/secboot: fix NULL pointer dereference
The msgqueue pointer validity should be checked by its owner, not by the
msgqueue code itself to avoid this situation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-17 12:06:58 +10:00
Alexandre Courbot
b62880f796 drm/nouveau/core: add SEC2 engine
SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00